segled.v

CPLD VHDL 数码管程序

module segled(seg,dig,clk);
	output [8:1]seg;
	output [6:1]dig;
	input clk;
	
	reg[8:1] seg_reg;
    reg[6:1] dig_reg;
	reg[6:1] dig_regn;

always@(posedge clk)
	begin 
		dig_reg = dig_reg<<1;
		if(dig_reg== 6'h00) dig_reg= 6'h01;
		dig_regn = ~dig_reg;
	end

always@(dig_regn)
begin
	case(dig_reg)
		6'h01:seg_reg=8'b00100100;
		6'h02:seg_reg=8'b11101010;
		6'h04:seg_reg=8'b11100110;
		6'h08:seg_reg=8'b01110100;
		6'h10:seg_reg=8'b11010110;
		6'h20:seg_reg=8'b11011110;
	endcase
end

assign seg = seg_reg;
assign dig = dig_regn;
endmodule