tffe_v.vhd

CPLD VHDL 数码管程序

LIBRARY ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.maxplus2.all;

ENTITY tffe_v IS
		PORT(T,Clk,Clrn,Prn,Ena	: IN	STD_LOGIC;
			 Q: OUT	STD_LOGIC);
END tffe_v;

architecture a of tffe_v is
	begin
	rod1:TFFE
		 PORT MAP(T,Clk,Clrn,Prn,Ena,Q);
	end a;