📄 waterled.rpt
字号:
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------- LC109 led3
| +--------- LC107 led4
| | +------- LC105 led5
| | | +----- LC104 led6
| | | | +--- LC101 led7
| | | | | +- LC99 led8
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'G'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
83 -> - - - - - - | - - - - - - - - | <-- clk
LC121-> * * * * * * | - - - - - - * * | <-- lreg8
LC122-> * * * * * * | - - - - - - * * | <-- lreg7
LC120-> * * * * * * | - - - - - - * * | <-- lreg6
LC119-> * * * * * * | - - - - - - * * | <-- lreg5
LC118-> * * * * * * | - - - - - - * * | <-- lreg4
LC116-> * * * * * * | - - - - - - * * | <-- lreg3
LC114-> * * * * * * | - - - - - - * * | <-- lreg2
LC113-> * * * * * * | - - - - - - * * | <-- lreg1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\alter board\document\sourcecode\cpld\waterled\waterled.rpt
waterled
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------- LC117 led1
| +----------------- LC115 led2
| | +--------------- LC121 lreg8
| | | +------------- LC122 lreg7
| | | | +----------- LC120 lreg6
| | | | | +--------- LC119 lreg5
| | | | | | +------- LC118 lreg4
| | | | | | | +----- LC116 lreg3
| | | | | | | | +--- LC114 lreg2
| | | | | | | | | +- LC113 lreg1
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC121-> * * * * * * * * * * | - - - - - - * * | <-- lreg8
LC122-> * * * * * * * * * * | - - - - - - * * | <-- lreg7
LC120-> * * * * * * * * * * | - - - - - - * * | <-- lreg6
LC119-> * * * * * * * * * * | - - - - - - * * | <-- lreg5
LC118-> * * * * * * * * * * | - - - - - - * * | <-- lreg4
LC116-> * * * * * * * * * * | - - - - - - * * | <-- lreg3
LC114-> * * * * * * * * * * | - - - - - - * * | <-- lreg2
LC113-> * * * * * * * * * * | - - - - - - * * | <-- lreg1
Pin
83 -> - - - - - - - - - - | - - - - - - - - | <-- clk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\alter board\document\sourcecode\cpld\waterled\waterled.rpt
waterled
** EQUATIONS **
clk : INPUT;
-- Node name is 'led1' = 'lregn1'
-- Equation name is 'led1', location is LC117, type is output.
led1 = DFFE( _EQ001 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is 'led2' = 'lregn2'
-- Equation name is 'led2', location is LC115, type is output.
led2 = DFFE( _EQ002 $ !lreg1, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is 'led3' = 'lregn3'
-- Equation name is 'led3', location is LC109, type is output.
led3 = DFFE( _EQ003 $ !lreg2, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is 'led4' = 'lregn4'
-- Equation name is 'led4', location is LC107, type is output.
led4 = DFFE( _EQ004 $ !lreg3, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is 'led5' = 'lregn5'
-- Equation name is 'led5', location is LC105, type is output.
led5 = DFFE( _EQ005 $ !lreg4, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is 'led6' = 'lregn6'
-- Equation name is 'led6', location is LC104, type is output.
led6 = DFFE( _EQ006 $ !lreg5, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is 'led7' = 'lregn7'
-- Equation name is 'led7', location is LC101, type is output.
led7 = DFFE( _EQ007 $ !lreg6, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is 'led8' = 'lregn8'
-- Equation name is 'led8', location is LC099, type is output.
led8 = DFFE( _EQ008 $ !lreg7, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is ':65' = 'lreg1'
-- Equation name is 'lreg1', location is LC113, type is buried.
lreg1 = DFFE( _EQ009 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is ':64' = 'lreg2'
-- Equation name is 'lreg2', location is LC114, type is buried.
lreg2 = DFFE( _EQ010 $ lreg1, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is ':63' = 'lreg3'
-- Equation name is 'lreg3', location is LC116, type is buried.
lreg3 = DFFE( _EQ011 $ lreg2, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is ':62' = 'lreg4'
-- Equation name is 'lreg4', location is LC118, type is buried.
lreg4 = DFFE( _EQ012 $ lreg3, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is ':61' = 'lreg5'
-- Equation name is 'lreg5', location is LC119, type is buried.
lreg5 = DFFE( _EQ013 $ lreg4, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is ':60' = 'lreg6'
-- Equation name is 'lreg6', location is LC120, type is buried.
lreg6 = DFFE( _EQ014 $ lreg5, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is ':59' = 'lreg7'
-- Equation name is 'lreg7', location is LC122, type is buried.
lreg7 = DFFE( _EQ015 $ lreg6, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Node name is ':58' = 'lreg8'
-- Equation name is 'lreg8', location is LC121, type is buried.
lreg8 = DFFE( _EQ016 $ lreg7, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !lreg1 & !lreg2 & !lreg3 & !lreg4 & !lreg5 & !lreg6 & !lreg7 &
!lreg8;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Informatione:\alter board\document\sourcecode\cpld\waterled\waterled.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,816K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -