waterled.v

CPLD VHDL 数码管程序

module waterled(led,clk);
	output [8:1] led;
    input  clk;

	reg[9:1] lreg;
    reg[9:1] lregn;

always@(posedge clk)
	begin 
		lreg = lreg<<1;
		if(lreg == 9'h000) lreg = 9'h1ff;
		lregn = ~lreg;
	end
	
    assign led = lregn[8:1];
endmodule