dffe_v.vhd

CPLD VHDL 数码管程序

LIBRARY ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.maxplus2.all;

ENTITY dffe_v IS
		PORT(D,Clk,Clrn,Prn,Ena	: IN	STD_LOGIC;
			 Q: OUT	STD_LOGIC);
END dffe_v;

architecture a of dffe_v is
	begin
	rod1:DFFE
		 PORT MAP(D =>D,CLK=>Clk,CLRN=>Clrn,PRN=>Prn,ENA=>Ena,Q=>Q);
	end a;