organ.v

来自「CPLD VHDL 数码管程序」· Verilog 代码 · 共 54 行

module organ(keyin,clk,spk);
	input clk;
	input [7:1] keyin;
	output spk;

	reg spk_reg;
    reg [19:0] count,count_end;

always @(posedge clk)
begin
	count = count+1;
	if((count==count_end)&(!(count_end==20'hffff0)))
		begin
			count=20'h00000;
			spk_reg=!spk_reg;
		end

	else if(count_end==20'hffff0) spk_reg=0;
end

always@(keyin)
begin
	case(keyin)
		7'b0000001:count_end=20'h2947;
		7'b0000010:count_end=20'h24c6;
		7'b0000100:count_end=20'h20c3;
		7'b0001000:count_end=20'h1eec;
		7'b0010000:count_end=20'h1b8d;
		7'b0100000:count_end=20'h15de;
		default:count_end=20'hffff0;
	endcase
end

assign spk=spk_reg;
endmodule