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📄 organ.rpt

📁 CPLD VHDL 数码管程序
💻 RPT
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_LC091   = LCELL( _EQ055 $ !_LC103);
  _EQ055 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X003  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 &  keyin5 & !keyin6 & 
             !keyin7);
  _X004  = EXP( keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X005  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 &  keyin6 & 
             !keyin7);
  _X006  = EXP(!keyin1 & !keyin2 &  keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);

-- Node name is '~242~1' 
-- Equation name is '~242~1', location is LC095, type is buried.
-- synthesized logic cell 
_LC095   = LCELL( _EQ056 $ !_LC104);
  _EQ056 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X003  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 &  keyin5 & !keyin6 & 
             !keyin7);
  _X004  = EXP( keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X005  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 &  keyin6 & 
             !keyin7);
  _X006  = EXP(!keyin1 & !keyin2 &  keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);

-- Node name is '~243~1' 
-- Equation name is '~243~1', location is LC084, type is buried.
-- synthesized logic cell 
_LC084   = LCELL( _EQ057 $ !_LC105);
  _EQ057 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X003  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 &  keyin5 & !keyin6 & 
             !keyin7);
  _X004  = EXP( keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X005  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 &  keyin6 & 
             !keyin7);
  _X006  = EXP(!keyin1 & !keyin2 &  keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);

-- Node name is '~244~1' 
-- Equation name is '~244~1', location is LC092, type is buried.
-- synthesized logic cell 
_LC092   = LCELL( _EQ058 $ !_LC107);
  _EQ058 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X003  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 &  keyin5 & !keyin6 & 
             !keyin7);
  _X004  = EXP( keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X005  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 &  keyin6 & 
             !keyin7);
  _X006  = EXP(!keyin1 & !keyin2 &  keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);

-- Node name is '~245~1' 
-- Equation name is '~245~1', location is LC093, type is buried.
-- synthesized logic cell 
_LC093   = LCELL( _EQ059 $ !_LC108);
  _EQ059 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X003  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 &  keyin5 & !keyin6 & 
             !keyin7);
  _X004  = EXP( keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X005  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 &  keyin6 & 
             !keyin7);
  _X006  = EXP(!keyin1 & !keyin2 &  keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);

-- Node name is '~246~1' 
-- Equation name is '~246~1', location is LC094, type is buried.
-- synthesized logic cell 
_LC094   = LCELL( _EQ060 $ !_LC106);
  _EQ060 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X003  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 &  keyin5 & !keyin6 & 
             !keyin7);
  _X004  = EXP( keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X005  = EXP(!keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 &  keyin6 & 
             !keyin7);
  _X006  = EXP(!keyin1 & !keyin2 &  keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);

-- Node name is '~247~1' 
-- Equation name is '~247~1', location is LC099, type is buried.
-- synthesized logic cell 
_LC099   = LCELL( _EQ061 $  _EQ062);
  _EQ061 = !keyin1 & !keyin2 & !keyin3 & !keyin4 &  keyin5 & !keyin6 & 
             !keyin7 &  _X001 &  _X002
         # !keyin1 & !keyin2 &  keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7 &  _X001 &  _X002
         #  keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7 &  _X001 &  _X002
         # !keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 &  keyin6 & 
             !keyin7 &  _X001 &  _X002;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _EQ062 =  _X001 &  _X002;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);

-- Node name is '~271~1' 
-- Equation name is '~271~1', location is LC050, type is buried.
-- synthesized logic cell 
_LC050   = LCELL( _EQ063 $  GND);
  _EQ063 =  _LC081 &  _LC082 &  _LC083 &  _LC084 &  _LC085 &  _LC087 & 
              _LC088 &  _LC089 &  _LC090 &  _LC091 &  _LC092 &  _LC093 & 
              _LC094 &  _LC095 &  _LC096 &  _LC097 &  _LC098 & !_LC099 & 
              _LC102 &  _LC110 &  _LC111;

-- Node name is '~396~1' 
-- Equation name is '~396~1', location is LC109, type is buried.
-- synthesized logic cell 
_LC109   = LCELL( _EQ064 $  _EQ065);
  _EQ064 = !keyin1 & !keyin2 & !keyin3 & !keyin4 &  keyin5 & !keyin6 & 
             !keyin7 &  _X001 &  _X002
         # !keyin1 & !keyin2 &  keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7 &  _X001 &  _X002
         #  keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7 &  _X001 &  _X002
         # !keyin1 & !keyin2 & !keyin3 & !keyin4 & !keyin5 &  keyin6 & 
             !keyin7 &  _X001 &  _X002;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _EQ065 =  _X001 &  _X002;
  _X001  = EXP(!keyin1 & !keyin2 & !keyin3 &  keyin4 & !keyin5 & !keyin6 & 
             !keyin7);
  _X002  = EXP(!keyin1 &  keyin2 & !keyin3 & !keyin4 & !keyin5 & !keyin6 & 
             !keyin7);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs F, G
--    _X002 occurs in LABs F, G
--    _X003 occurs in LABs F, G
--    _X004 occurs in LABs F, G
--    _X005 occurs in LABs F, G




Project Information                             d:\source\cpld\organ\organ.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,782K

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