count10_v.vhd

CPLD VHDL 数码管程序

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY count10_v IS
		PORT(Load,Ent,Enp,Clrn,Clk	: IN	STD_LOGIC;
			 D: IN std_logic_vector(3 downto 0);
			 Q: OUT std_logic_vector(3 downto 0);
			 Co:out std_logic);
END count10_v;

architecture a of count10_v is
	begin
		process(Clk)
			variable tmp :std_logic_vector(3 downto 0);
		begin
			if(Clk'event and Clk='1') then
				if Clrn='0' then tmp:="0000";
				elsif Load='0' then tmp:=D;
				elsif (Ent and Enp)='1' then
					if tmp="1001" then tmp:="0000";
					else tmp:=tmp+1;
					end if;
				end if;

			end if;
			Q<=tmp; Co<=(tmp(0) and tmp(3) and Ent);
		end process;
	end a;