mul.vhd

CPLD VHDL 数码管程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mul is
	port(A,B : IN std_logic_vector(2 downto 0);
		 M	 : out std_logic_vector(5 downto 0));
end mul;
architecture a of mul is
	signal temp1:std_logic_vector(2 downto 0);
	signal temp2:std_logic_vector(3 downto 0);
	signal temp3:std_logic_vector(4 downto 0);
	begin
			temp1 <=a when B(0)='1' else "000";
			temp2 <= (A & '0') when B(1)='1' else "0000";
			temp3 <= (A & "00") when B(2)='1' else "00000";
			M <= temp1+temp2+('0' & temp3);
end a;