📄 mul.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------------- LC17 |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|gcp2
| +------------------------- LC25 |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|g4
| | +----------------------- LC29 |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|ps2
| | | +--------------------- LC26 |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|result_node2
| | | | +------------------- LC28 |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|result_node3
| | | | | +----------------- LC31 |LPM_ADD_SUB:160|addcore:adder|addcore:adder0|g4
| | | | | | +--------------- LC27 |LPM_ADD_SUB:160|addcore:adder|addcore:adder0|ps3
| | | | | | | +------------- LC20 |LPM_ADD_SUB:160|datab_node4
| | | | | | | | +----------- LC18 M0
| | | | | | | | | +--------- LC24 M1
| | | | | | | | | | +------- LC21 M2
| | | | | | | | | | | +----- LC19 M3
| | | | | | | | | | | | +--- LC22 M4
| | | | | | | | | | | | | +- LC23 M5
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> - - - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|gcp2
LC25 -> - - - - - - - - - - - - * * | - * | <-- |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|g4
LC29 -> * - - * - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|ps2
LC26 -> - - - - - * - - - - * * - - | - * | <-- |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|result_node2
LC28 -> - - - - - * * - - - - * - - | - * | <-- |LPM_ADD_SUB:153|addcore:adder|addcore:adder0|result_node3
LC31 -> - - - - - - - - - - - - * * | - * | <-- |LPM_ADD_SUB:160|addcore:adder|addcore:adder0|g4
LC27 -> - - - - - * - - - - - * - - | - * | <-- |LPM_ADD_SUB:160|addcore:adder|addcore:adder0|ps3
LC20 -> - - - - - - - - - - - - * * | - * | <-- |LPM_ADD_SUB:160|datab_node4
Pin
4 -> * - - * - * - - * * * * - - | - * | <-- A0
6 -> * * * * - * * - - * - * * * | - * | <-- A1
8 -> * * * * * - - * - - - - * * | - * | <-- A2
9 -> * * * * - - - - * * - - * * | - * | <-- B0
11 -> * * * * * - - - - * - - * * | - * | <-- B1
5 -> - - - - - * * * - - * * * * | - * | <-- B2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\source\aaaaaa\sourcecode\cpld\mul_vhdl\mul.rpt
mul
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
-- Node name is 'M0'
-- Equation name is 'M0', location is LC018, type is output.
M0 = LCELL( _EQ001 $ GND);
_EQ001 = A0 & B0;
-- Node name is 'M1'
-- Equation name is 'M1', location is LC024, type is output.
M1 = LCELL( _EQ002 $ _EQ003);
_EQ002 = A1 & B0;
_EQ003 = A0 & B1;
-- Node name is 'M2'
-- Equation name is 'M2', location is LC021, type is output.
M2 = LCELL( _EQ004 $ _LC026);
_EQ004 = A0 & B2;
-- Node name is 'M3'
-- Equation name is 'M3', location is LC019, type is output.
M3 = LCELL( _EQ005 $ _EQ006);
_EQ005 = !_LC027 & _X001;
_X001 = EXP( A1 & B2 & _LC028);
_EQ006 = A0 & B2 & _LC026;
-- Node name is 'M4'
-- Equation name is 'M4', location is LC022, type is output.
M4 = LCELL( _EQ007 $ _LC031);
_EQ007 = _X002 & _X003;
_X002 = EXP( A1 & A2 & B0 & B1 & B2);
_X003 = EXP(!_LC020 & !_LC025);
-- Node name is 'M5'
-- Equation name is 'M5', location is LC023, type is output.
M5 = LCELL( _EQ008 $ GND);
_EQ008 = A1 & A2 & B0 & B1 & B2
# _LC031 & _X003;
_X003 = EXP(!_LC020 & !_LC025);
-- Node name is '|LPM_ADD_SUB:153|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC017', type is buried
_LC017 = LCELL( _EQ009 $ GND);
_EQ009 = A0 & A1 & B0 & B1 & !_LC029
# A1 & A2 & B0 & B1;
-- Node name is '|LPM_ADD_SUB:153|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( _EQ010 $ GND);
_EQ010 = A1 & A2 & B0 & B1;
-- Node name is '|LPM_ADD_SUB:153|addcore:adder|addcore:adder0|ps2' from file "addcore.tdf" line 150, column 7
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( _EQ011 $ _EQ012);
_EQ011 = A2 & B0 & _X004;
_X004 = EXP( A1 & B1);
_EQ012 = _X004;
_X004 = EXP( A1 & B1);
-- Node name is '|LPM_ADD_SUB:153|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( _EQ013 $ GND);
_EQ013 = A0 & A1 & A2 & B0 & B1
# A0 & A1 & B0 & B1 & _LC029
# !B0 & !_LC029 & _X005
# !A1 & !_LC029 & _X005
# !_LC029 & _X005 & _X006;
_X005 = EXP( A1 & A2 & B0 & B1);
_X006 = EXP( A0 & B1);
-- Node name is '|LPM_ADD_SUB:153|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( _EQ014 $ !_LC017);
_EQ014 = _X007;
_X007 = EXP( A2 & B1);
-- Node name is '|LPM_ADD_SUB:160|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( _EQ015 $ _EQ016);
_EQ015 = A1 & B2 & _LC028;
_EQ016 = A0 & B2 & _LC026 & !_LC027 & _X001;
_X001 = EXP( A1 & B2 & _LC028);
-- Node name is '|LPM_ADD_SUB:160|addcore:adder|addcore:adder0|ps3' from file "addcore.tdf" line 150, column 7
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( _EQ017 $ GND);
_EQ017 = !_LC028 & _X008;
_X008 = EXP( A1 & B2);
-- Node name is '|LPM_ADD_SUB:160|datab_node4' from file "lpm_add_sub.tdf" line 114, column 14
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( _EQ018 $ GND);
_EQ018 = A2 & B2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\source\aaaaaa\sourcecode\cpld\mul_vhdl\mul.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,824K
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