keyinput.rpt

CPLD VHDL 数码管程序

 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  64     99    G     OUTPUT      t        0      0   0    1    0    0    0  led1
  65    101    G     OUTPUT      t        0      0   0    1    0    0    0  led2
  67    104    G     OUTPUT      t        0      0   0    1    0    0    0  led3
  68    105    G     OUTPUT      t        0      0   0    1    0    0    0  led4
  69    107    G     OUTPUT      t        0      0   0    1    0    0    0  led5
  70    109    G     OUTPUT      t        0      0   0    1    0    0    0  led6
  73    115    H     OUTPUT      t        0      0   0    1    0    0    0  led7
  74    117    H     OUTPUT      t        0      0   0    1    0    0    0  led8


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:e:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
keyinput

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                     Logic cells placed in LAB 'G'
        +----------- LC99 led1
        | +--------- LC101 led2
        | | +------- LC104 led3
        | | | +----- LC105 led4
        | | | | +--- LC107 led5
        | | | | | +- LC109 led6
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'G'
LC      | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':

Pin
63   -> * - - - - - | - - - - - - * - | <-- sw1
61   -> - * - - - - | - - - - - - * - | <-- sw2
60   -> - - * - - - | - - - - - - * - | <-- sw3
58   -> - - - * - - | - - - - - - * - | <-- sw4
57   -> - - - - * - | - - - - - - * - | <-- sw5
56   -> - - - - - * | - - - - - - * - | <-- sw6


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:e:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
keyinput

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

             Logic cells placed in LAB 'H'
        +--- LC115 led7
        | +- LC117 led8
        | | 
        | |   Other LABs fed by signals
        | |   that feed LAB 'H'
LC      | | | A B C D E F G H |     Logic cells that feed LAB 'H':

Pin
55   -> * - | - - - - - - - * | <-- sw7
54   -> - * | - - - - - - - * | <-- sw8


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:e:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
keyinput

** EQUATIONS **

sw1      : INPUT;
sw2      : INPUT;
sw3      : INPUT;
sw4      : INPUT;
sw5      : INPUT;
sw6      : INPUT;
sw7      : INPUT;
sw8      : INPUT;

-- Node name is 'led1' 
-- Equation name is 'led1', location is LC099, type is output.
 led1    = LCELL( sw1 $  GND);

-- Node name is 'led2' 
-- Equation name is 'led2', location is LC101, type is output.
 led2    = LCELL( sw2 $  GND);

-- Node name is 'led3' 
-- Equation name is 'led3', location is LC104, type is output.
 led3    = LCELL( sw3 $  GND);

-- Node name is 'led4' 
-- Equation name is 'led4', location is LC105, type is output.
 led4    = LCELL( sw4 $  GND);

-- Node name is 'led5' 
-- Equation name is 'led5', location is LC107, type is output.
 led5    = LCELL( sw5 $  GND);

-- Node name is 'led6' 
-- Equation name is 'led6', location is LC109, type is output.
 led6    = LCELL( sw6 $  GND);

-- Node name is 'led7' 
-- Equation name is 'led7', location is LC115, type is output.
 led7    = LCELL( sw7 $  GND);

-- Node name is 'led8' 
-- Equation name is 'led8', location is LC117, type is output.
 led8    = LCELL( sw8 $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Informatione:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,853K