📄 keyinput.rpt
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Project Informatione:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/14/2005 09:23:23
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
keyinput EPM7128SLC84-15 8 8 0 8 0 6 %
User Pins: 8 8 0
Project Informatione:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
keyinput@64 led1
keyinput@65 led2
keyinput@67 led3
keyinput@68 led4
keyinput@69 led5
keyinput@70 led6
keyinput@73 led7
keyinput@74 led8
keyinput@63 sw1
keyinput@61 sw2
keyinput@60 sw3
keyinput@58 sw4
keyinput@57 sw5
keyinput@56 sw6
keyinput@55 sw7
keyinput@54 sw8
Device-Specific Information:e:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
keyinput
***** Logic for device 'keyinput' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R R R R R
E E E E E E E E E E E E E
S S S S S S S V S S S S S S
E E E E E E E C E E E V E E E
R R R R R R R C R R R C R R R
V V V V G V V V I G G G G G V V V C V V V
E E E E N E E E N N N N N N E E E I E E E
D D D D D D D D T D D D D D D D D O D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
RESERVED | 12 74 | led8
VCCIO | 13 73 | led7
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | led6
RESERVED | 17 69 | led5
RESERVED | 18 68 | led4
GND | 19 67 | led3
RESERVED | 20 66 | VCCIO
RESERVED | 21 65 | led2
RESERVED | 22 EPM7128SLC84-15 64 | led1
#TMS | 23 63 | sw1
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | sw2
VCCIO | 26 60 | sw3
RESERVED | 27 59 | GND
RESERVED | 28 58 | sw4
RESERVED | 29 57 | sw5
RESERVED | 30 56 | sw6
RESERVED | 31 55 | sw7
GND | 32 54 | sw8
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V R R R G V R R R G R R R R R V
E E E E E C E E E N C E E E N E E E E E C
S S S S S C S S S D C S S S D S S S S S C
E E E E E I E E E I E E E E E E E E I
R R R R R O R R R N R R R R R R R R O
V V V V V V V V T V V V V V V V V
E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
keyinput
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
G: LC97 - LC112 6/16( 37%) 8/ 8(100%) 0/16( 0%) 6/36( 16%)
H: LC113 - LC128 2/16( 12%) 2/ 8( 25%) 0/16( 0%) 2/36( 5%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 20/64 ( 31%)
Total logic cells used: 8/128 ( 6%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 8/128 ( 6%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 1.00
Total fan-in: 8
Total input pins required: 8
Total fast input logic cells required: 0
Total output pins required: 8
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 8
Total flipflops required: 0
Total product terms required: 8
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information:e:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
keyinput
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
63 (97) (G) INPUT 0 0 0 0 0 1 0 sw1
61 (94) (F) INPUT 0 0 0 0 0 1 0 sw2
60 (93) (F) INPUT 0 0 0 0 0 1 0 sw3
58 (91) (F) INPUT 0 0 0 0 0 1 0 sw4
57 (88) (F) INPUT 0 0 0 0 0 1 0 sw5
56 (86) (F) INPUT 0 0 0 0 0 1 0 sw6
55 (85) (F) INPUT 0 0 0 0 0 1 0 sw7
54 (83) (F) INPUT 0 0 0 0 0 1 0 sw8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:e:\alter board\document\sourcecode\cpld\keyinput\keyinput.rpt
keyinput
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
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