divider_v.vhd

CPLD VHDL 数码管程序

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY divider_v IS
		PORT(CLKI	: IN	STD_LOGIC;
			 CLKO   : out std_logic);
END divider_v;

architecture a of divider_v is
	signal cou: std_logic_vector(3 downto 0);
	begin
		process
		begin
			wait until CLKI ='1';
			cou <= cou+1;			
		end process;
		CLKO <= cou(3);
	end a;