s_term.tdf

FPGA开发光盘各章节实例的设计工程与源码

include "p_s";
parameters
(
	in_width = 12,
	term_wid = 16       --3
);

subdesign s_term
(
	clk									: input;
	clr									: input = vcc;
	data_in[term_wid..1][in_width..1] 	: input;
	load								: input;           --= gnd;
	rom_ad[term_wid..1]					: output;
)

variable
regs[term_wid..1]	:p_s with (width = in_width );

begin
	regs[].clk = clk;
	regs[].clr = clr;
	regs[].load_n = load;
	
	for i in 1 to term_wid generate
		regs[i].parallel_in[] = data_in[i][];
	end generate;
	
	rom_ad[] = regs[].serial_out;
	
end;