filter.hif

FPGA开发光盘各章节实例的设计工程与源码

-1
3
data_in10_7
-1
3
data_in10_6
-1
3
data_in10_5
-1
3
data_in10_4
-1
3
data_in10_3
-1
3
data_in10_2
-1
3
data_in10_12
-1
3
data_in10_11
-1
3
data_in10_10
-1
3
data_in10_1
-1
3
clr
-1
3
clk
-1
3
}
# include_file {
p_s.inc
8f1111421243f5090cae959e8795a5
}
# hierarchies {
s_term:p_s_c
}
# end
# entity
p_s
# storage
db|filter.(4).cnf
db|filter.(4).cnf
# case_insensitive
# source_file
p_s.tdf
919c978b32d1d27a8c7011323d3a48fc
6
# user_parameter {
width
12
PARAMETER_UNKNOWN
USR
}
# used_port {
serial_out
-1
3
parallel_in9
-1
3
parallel_in8
-1
3
parallel_in7
-1
3
parallel_in6
-1
3
parallel_in5
-1
3
parallel_in4
-1
3
parallel_in3
-1
3
parallel_in2
-1
3
parallel_in12
-1
3
parallel_in11
-1
3
parallel_in10
-1
3
parallel_in1
-1
3
load_n
-1
3
clr
-1
3
clk
-1
3
}
# hierarchies {
s_term:p_s_c|p_s:regs[16]
s_term:p_s_c|p_s:regs[15]
s_term:p_s_c|p_s:regs[14]
s_term:p_s_c|p_s:regs[13]
s_term:p_s_c|p_s:regs[12]
s_term:p_s_c|p_s:regs[11]
s_term:p_s_c|p_s:regs[10]
s_term:p_s_c|p_s:regs[9]
s_term:p_s_c|p_s:regs[8]
s_term:p_s_c|p_s:regs[7]
s_term:p_s_c|p_s:regs[6]
s_term:p_s_c|p_s:regs[5]
s_term:p_s_c|p_s:regs[4]
s_term:p_s_c|p_s:regs[3]
s_term:p_s_c|p_s:regs[2]
s_term:p_s_c|p_s:regs[1]
}
# end
# entity
altsyncram
# storage
db|filter.(6).cnf
db|filter.(6).cnf
# case_insensitive
# source_file
c:|altera|61|quartus|libraries|megafunctions|altsyncram.tdf
82b9e86c1df4d3a925c3859b8da0bf
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_UNKNOWN
USR
WIDTHAD_A
16
PARAMETER_UNKNOWN
USR
NUMWORDS_A
65536
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
E:/w_fir/Quartus/rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_pb21
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|61|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|61|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
c:|altera|61|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|61|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|61|quartus|libraries|megafunctions|aglobal61.inc
b513fb574ceb8f5886cd4ba429e82ec
c:|altera|61|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|61|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|61|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|61|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
}
# end
# entity
filter
# storage
db|filter.(0).cnf
db|filter.(0).cnf
# case_insensitive
# source_file
filter.tdf
d963ff148fcc425c8a95938de6f8e1df
6
# user_parameter {
tap
16
PARAMETER_UNKNOWN
DEF
x_wid
12
PARAMETER_UNKNOWN
DEF
x_pre
10
PARAMETER_UNKNOWN
DEF
coef_wid
16
PARAMETER_UNKNOWN
DEF
coef_pre
15
PARAMETER_UNKNOWN
DEF
z_wid
18
PARAMETER_UNKNOWN
DEF
z_pre
15
PARAMETER_UNKNOWN
DEF
pipeline
yes
PARAMETER_UNKNOWN
DEF
}
# used_port {
0
-1
0
}
# include_file {
p_s.inc
8f1111421243f5090cae959e8795a5
accumulator.inc
39afd96a42e6ad7c3b7a3d9c030f3ee
s_term.inc
8554868fceea34e59971f3d8898e344b
filter_shift.inc
8a955ab2f4a836df9de5c351da4b5795
filter_coef.inc
2048c33dc284929a58d93d82312cf8f
filter_con.inc
5b7a302fded12d3be25488c0a3a2b9e1
}
# hierarchies {
|
}
# end
# entity
filter_coef
# storage
db|filter.(5).cnf
db|filter.(5).cnf
# case_insensitive
# source_file
filter_coef.tdf
8afa1ef984a0437b3a9cc1f4e5992d97
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
address9
-1
3
address8
-1
3
address7
-1
3
address6
-1
3
address5
-1
3
address4
-1
3
address3
-1
3
address2
-1
3
address15
-1
3
address14
-1
3
address13
-1
3
address12
-1
3
address11
-1
3
address10
-1
3
address1
-1
3
address0
-1
3
}
# include_file {
altsyncram.inc
9dd61d7a88309eb03dcbab49e389fcc
}
# hierarchies {
filter_coef:rom_coef
}
# end
# entity
altsyncram
# storage
db|filter.(7).cnf
db|filter.(7).cnf
# case_insensitive
# source_file
c:|altera|61|quartus|libraries|megafunctions|altsyncram.tdf
82b9e86c1df4d3a925c3859b8da0bf
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_UNKNOWN
USR
WIDTHAD_A
16
PARAMETER_UNKNOWN
USR
NUMWORDS_A
65536
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
wrom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_v331
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|61|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|61|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
c:|altera|61|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|61|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|61|quartus|libraries|megafunctions|aglobal61.inc
b513fb574ceb8f5886cd4ba429e82ec
c:|altera|61|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|61|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|61|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|61|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
}
# hierarchies {
filter_coef:rom_coef|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_v331
# storage
db|filter.(8).cnf
db|filter.(8).cnf
# case_insensitive
# source_file
db|altsyncram_v331.tdf
52c2f9995298f3de9a8bb2caf17ede6
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
wrom.mif
2bceabb61fdd77d110dd5e5025922
}
# hierarchies {
filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated
}
# end
# entity
mux_8fb
# storage
db|filter.(9).cnf
db|filter.(9).cnf
# case_insensitive
# source_file
db|mux_8fb.tdf
c215aedecb581d963d51a15f944c6
6
# used_port {
sel3
-1
3
sel2
-1
3
sel1
-1
3
sel0
-1
3
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data99
-1
3
data98
-1
3
data97
-1
3
data96
-1
3
data95
-1
3
data94
-1
3
data93
-1
3
data92
-1
3
data91
-1
3
data90
-1
3
data9
-1
3
data89
-1
3
data88
-1
3
data87
-1
3
data86
-1
3
data85
-1
3
data84
-1
3
data83
-1
3
data82
-1
3
data81
-1
3
data80
-1
3
data8
-1
3
data79
-1
3
data78
-1
3
data77
-1
3
data76
-1
3
data75
-1
3
data74
-1
3
data73
-1
3
data72
-1
3
data71
-1
3
data70
-1
3
data7
-1
3
data69
-1
3
data68
-1
3
data67
-1
3
data66
-1
3
data65
-1
3
data64
-1
3
data63
-1
3
data62
-1
3
data61
-1
3