filter.hier_info

FPGA开发光盘各章节实例的设计工程与源码

clr => reg[3].ACLR
clr => reg[2].ACLR
clr => reg[1].ACLR


|filter|s_term:p_s_c|p_s:regs[2]
serial_out <= reg[1].DB_MAX_OUTPUT_PORT_TYPE
clk => reg[12].CLK
clk => reg[11].CLK
clk => reg[10].CLK
clk => reg[9].CLK
clk => reg[8].CLK
clk => reg[7].CLK
clk => reg[6].CLK
clk => reg[5].CLK
clk => reg[4].CLK
clk => reg[3].CLK
clk => reg[2].CLK
clk => reg[1].CLK
clr => reg[12].ACLR
clr => reg[11].ACLR
clr => reg[10].ACLR
clr => reg[9].ACLR
clr => reg[8].ACLR
clr => reg[7].ACLR
clr => reg[6].ACLR
clr => reg[5].ACLR
clr => reg[4].ACLR
clr => reg[3].ACLR
clr => reg[2].ACLR
clr => reg[1].ACLR


|filter|s_term:p_s_c|p_s:regs[1]
serial_out <= reg[1].DB_MAX_OUTPUT_PORT_TYPE
clk => reg[12].CLK
clk => reg[11].CLK
clk => reg[10].CLK
clk => reg[9].CLK
clk => reg[8].CLK
clk => reg[7].CLK
clk => reg[6].CLK
clk => reg[5].CLK
clk => reg[4].CLK
clk => reg[3].CLK
clk => reg[2].CLK
clk => reg[1].CLK
clr => reg[12].ACLR
clr => reg[11].ACLR
clr => reg[10].ACLR
clr => reg[9].ACLR
clr => reg[8].ACLR
clr => reg[7].ACLR
clr => reg[6].ACLR
clr => reg[5].ACLR
clr => reg[4].ACLR
clr => reg[3].ACLR
clr => reg[2].ACLR
clr => reg[1].ACLR


|filter|filter_coef:rom_coef
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
address[12] => altsyncram:altsyncram_component.address_a[12]
address[13] => altsyncram:altsyncram_component.address_a[13]
address[14] => altsyncram:altsyncram_component.address_a[14]
address[15] => altsyncram:altsyncram_component.address_a[15]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]


|filter|filter_coef:rom_coef|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_v331:auto_generated.address_a[0]
address_a[1] => altsyncram_v331:auto_generated.address_a[1]
address_a[2] => altsyncram_v331:auto_generated.address_a[2]
address_a[3] => altsyncram_v331:auto_generated.address_a[3]
address_a[4] => altsyncram_v331:auto_generated.address_a[4]
address_a[5] => altsyncram_v331:auto_generated.address_a[5]
address_a[6] => altsyncram_v331:auto_generated.address_a[6]
address_a[7] => altsyncram_v331:auto_generated.address_a[7]
address_a[8] => altsyncram_v331:auto_generated.address_a[8]
address_a[9] => altsyncram_v331:auto_generated.address_a[9]
address_a[10] => altsyncram_v331:auto_generated.address_a[10]
address_a[11] => altsyncram_v331:auto_generated.address_a[11]
address_a[12] => altsyncram_v331:auto_generated.address_a[12]
address_a[13] => altsyncram_v331:auto_generated.address_a[13]
address_a[14] => altsyncram_v331:auto_generated.address_a[14]
address_a[15] => altsyncram_v331:auto_generated.address_a[15]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_v331:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_v331:auto_generated.q_a[0]
q_a[1] <= altsyncram_v331:auto_generated.q_a[1]
q_a[2] <= altsyncram_v331:auto_generated.q_a[2]
q_a[3] <= altsyncram_v331:auto_generated.q_a[3]
q_a[4] <= altsyncram_v331:auto_generated.q_a[4]
q_a[5] <= altsyncram_v331:auto_generated.q_a[5]
q_a[6] <= altsyncram_v331:auto_generated.q_a[6]
q_a[7] <= altsyncram_v331:auto_generated.q_a[7]
q_a[8] <= altsyncram_v331:auto_generated.q_a[8]
q_a[9] <= altsyncram_v331:auto_generated.q_a[9]
q_a[10] <= altsyncram_v331:auto_generated.q_a[10]
q_a[11] <= altsyncram_v331:auto_generated.q_a[11]
q_a[12] <= altsyncram_v331:auto_generated.q_a[12]
q_a[13] <= altsyncram_v331:auto_generated.q_a[13]
q_a[14] <= altsyncram_v331:auto_generated.q_a[14]
q_a[15] <= altsyncram_v331:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|filter|filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[0] => ram_block1a32.PORTAADDR
address_a[0] => ram_block1a33.PORTAADDR
address_a[0] => ram_block1a34.PORTAADDR
address_a[0] => ram_block1a35.PORTAADDR
address_a[0] => ram_block1a36.PORTAADDR
address_a[0] => ram_block1a37.PORTAADDR
address_a[0] => ram_block1a38.PORTAADDR
address_a[0] => ram_block1a39.PORTAADDR
address_a[0] => ram_block1a40.PORTAADDR
address_a[0] => ram_block1a41.PORTAADDR
address_a[0] => ram_block1a42.PORTAADDR
address_a[0] => ram_block1a43.PORTAADDR
address_a[0] => ram_block1a44.PORTAADDR
address_a[0] => ram_block1a45.PORTAADDR
address_a[0] => ram_block1a46.PORTAADDR
address_a[0] => ram_block1a47.PORTAADDR
address_a[0] => ram_block1a48.PORTAADDR
address_a[0] => ram_block1a49.PORTAADDR
address_a[0] => ram_block1a50.PORTAADDR
address_a[0] => ram_block1a51.PORTAADDR
address_a[0] => ram_block1a52.PORTAADDR
address_a[0] => ram_block1a53.PORTAADDR
address_a[0] => ram_block1a54.PORTAADDR
address_a[0] => ram_block1a55.PORTAADDR
address_a[0] => ram_block1a56.PORTAADDR
address_a[0] => ram_block1a57.PORTAADDR
address_a[0] => ram_block1a58.PORTAADDR
address_a[0] => ram_block1a59.PORTAADDR
address_a[0] => ram_block1a60.PORTAADDR
address_a[0] => ram_block1a61.PORTAADDR
address_a[0] => ram_block1a62.PORTAADDR
address_a[0] => ram_block1a63.PORTAADDR
address_a[0] => ram_block1a64.PORTAADDR
address_a[0] => ram_block1a65.PORTAADDR
address_a[0] => ram_block1a66.PORTAADDR
address_a[0] => ram_block1a67.PORTAADDR
address_a[0] => ram_block1a68.PORTAADDR
address_a[0] => ram_block1a69.PORTAADDR
address_a[0] => ram_block1a70.PORTAADDR
address_a[0] => ram_block1a71.PORTAADDR
address_a[0] => ram_block1a72.PORTAADDR
address_a[0] => ram_block1a73.PORTAADDR
address_a[0] => ram_block1a74.PORTAADDR
address_a[0] => ram_block1a75.PORTAADDR
address_a[0] => ram_block1a76.PORTAADDR
address_a[0] => ram_block1a77.PORTAADDR
address_a[0] => ram_block1a78.PORTAADDR
address_a[0] => ram_block1a79.PORTAADDR
address_a[0] => ram_block1a80.PORTAADDR
address_a[0] => ram_block1a81.PORTAADDR
address_a[0] => ram_block1a82.PORTAADDR
address_a[0] => ram_block1a83.PORTAADDR
address_a[0] => ram_block1a84.PORTAADDR
address_a[0] => ram_block1a85.PORTAADDR
address_a[0] => ram_block1a86.PORTAADDR
address_a[0] => ram_block1a87.PORTAADDR
address_a[0] => ram_block1a88.PORTAADDR
address_a[0] => ram_block1a89.PORTAADDR
address_a[0] => ram_block1a90.PORTAADDR
address_a[0] => ram_block1a91.PORTAADDR
address_a[0] => ram_block1a92.PORTAADDR
address_a[0] => ram_block1a93.PORTAADDR
address_a[0] => ram_block1a94.PORTAADDR
address_a[0] => ram_block1a95.PORTAADDR
address_a[0] => ram_block1a96.PORTAADDR
address_a[0] => ram_block1a97.PORTAADDR
address_a[0] => ram_block1a98.PORTAADDR
address_a[0] => ram_block1a99.PORTAADDR
address_a[0] => ram_block1a100.PORTAADDR
address_a[0] => ram_block1a101.PORTAADDR
address_a[0] => ram_block1a102.PORTAADDR
address_a[0] => ram_block1a103.PORTAADDR
address_a[0] => ram_block1a104.PORTAADDR
address_a[0] => ram_block1a105.PORTAADDR
address_a[0] => ram_block1a106.PORTAADDR
address_a[0] => ram_block1a107.PORTAADDR
address_a[0] => ram_block1a108.PORTAADDR
address_a[0] => ram_block1a109.PORTAADDR
address_a[0] => ram_block1a110.PORTAADDR
address_a[0] => ram_block1a111.PORTAADDR
address_a[0] => ram_block1a112.PORTAADDR
address_a[0] => ram_block1a113.PORTAADDR
address_a[0] => ram_block1a114.PORTAADDR
address_a[0] => ram_block1a115.PORTAADDR
address_a[0] => ram_block1a116.PORTAADDR
address_a[0] => ram_block1a117.PORTAADDR
address_a[0] => ram_block1a118.PORTAADDR
address_a[0] => ram_block1a119.PORTAADDR
address_a[0] => ram_block1a120.PORTAADDR
address_a[0] => ram_block1a121.PORTAADDR
address_a[0] => ram_block1a122.PORTAADDR
address_a[0] => ram_block1a123.PORTAADDR
address_a[0] => ram_block1a124.PORTAADDR
address_a[0] => ram_block1a125.PORTAADDR
address_a[0] => ram_block1a126.PORTAADDR
address_a[0] => ram_block1a127.PORTAADDR
address_a[0] => ram_block1a128.PORTAADDR
address_a[0] => ram_block1a129.PORTAADDR
address_a[0] => ram_block1a130.PORTAADDR
address_a[0] => ram_block1a131.PORTAADDR
address_a[0] => ram_block1a132.PORTAADDR
address_a[0] => ram_block1a133.PORTAADDR
address_a[0] => ram_block1a134.PORTAADDR
address_a[0] => ram_block1a135.PORTAADDR
address_a[0] => ram_block1a136.PORTAADDR
address_a[0] => ram_block1a137.PORTAADDR
address_a[0] => ram_block1a138.PORTAADDR
address_a[0] => ram_block1a139.PORTAADDR
address_a[0] => ram_block1a140.PORTAADDR
address_a[0] => ram_block1a141.PORTAADDR
address_a[0] => ram_block1a142.PORTAADDR
address_a[0] => ram_block1a143.PORTAADDR
address_a[0] => ram_block1a144.PORTAADDR
address_a[0] => ram_block1a145.PORTAADDR
address_a[0] => ram_block1a146.PORTAADDR
address_a[0] => ram_block1a147.PORTAADDR
address_a[0] => ram_block1a148.PORTAADDR
address_a[0] => ram_block1a149.PORTAADDR
address_a[0] => ram_block1a150.PORTAADDR
address_a[0] => ram_block1a151.PORTAADDR
address_a[0] => ram_block1a152.PORTAADDR
address_a[0] => ram_block1a153.PORTAADDR
address_a[0] => ram_block1a154.PORTAADDR
address_a[0] => ram_block1a155.PORTAADDR
address_a[0] => ram_block1a156.PORTAADDR
address_a[0] => ram_block1a157.PORTAADDR
address_a[0] => ram_block1a158.PORTAADDR
address_a[0] => ram_block1a159.PORTAADDR
address_a[0] => ram_block1a160.PORTAADDR
address_a[0] => ram_block1a161.PORTAADDR
address_a[0] => ram_block1a162.PORTAADDR
address_a[0] => ram_block1a163.PORTAADDR
address_a[0] => ram_block1a164.PORTAADDR
address_a[0] => ram_block1a165.PORTAADDR
address_a[0] => ram_block1a166.PORTAADDR
address_a[0] => ram_block1a167.PORTAADDR
address_a[0] => ram_block1a168.PORTAADDR
address_a[0] => ram_block1a169.PORTAADDR
address_a[0] => ram_block1a170.PORTAADDR
address_a[0] => ram_block1a171.PORTAADDR
address_a[0] => ram_block1a172.PORTAADDR
address_a[0] => ram_block1a173.PORTAADDR
address_a[0] => ram_block1a174.PORTAADDR
address_a[0] => ram_block1a175.PORTAADDR
address_a[0] => ram_block1a176.PORTAADDR
address_a[0] => ram_block1a177.PORTAADDR
address_a[0] => ram_block1a178.PORTAADDR
address_a[0] => ram_block1a179.PORTAADDR
address_a[0] => ram_block1a180.PORTAADDR
address_a[0] => ram_block1a181.PORTAADDR
address_a[0] => ram_block1a182.PORTAADDR
address_a[0] => ram_block1a183.PORTAADDR
address_a[0] => ram_block1a184.PORTAADDR
address_a[0] => ram_block1a185.PORTAADDR
address_a[0] => ram_block1a186.PORTAADDR
address_a[0] => ram_block1a187.PORTAADDR
address_a[0] => ram_block1a188.PORTAADDR
address_a[0] => ram_block1a189.PORTAADDR
address_a[0] => ram_block1a190.PORTAADDR
address_a[0] => ram_block1a191.PORTAADDR
address_a[0] => ram_block1a192.PORTAADDR
address_a[0] => ram_block1a193.PORTAADDR
address_a[0] => ram_block1a194.PORTAADDR
address_a[0] => ram_block1a195.PORTAADDR
address_a[0] => ram_block1a196.PORTAADDR
address_a[0] => ram_block1a197.PORTAADDR
address_a[0] => ram_block1a198.PORTAADDR
address_a[0] => ram_block1a199.PORTAADDR
address_a[0] => ram_block1a200.PORTAADDR
address_a[0] => ram_block1a201.PORTAADDR
address_a[0] => ram_block1a202.PORTAADDR
address_a[0] => ram_block1a203.PORTAADDR
address_a[0] => ram_block1a204.PORTAADDR
address_a[0] => ram_block1a205.PORTAADDR
address_a[0] => ram_block1a206.PORTAADDR
address_a[0] => ram_block1a207.PORTAADDR
address_a[0] => ram_block1a208.PORTAADDR
address_a[0] => ram_block1a209.PORTAADDR