filter.fit.eqn

FPGA开发光盘各章节实例的设计工程与源码

H1_ram_block[10][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[10][0]_clock_enable_0 = VCC;
H1_ram_block[10][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[10][0]_PORT_A_address_reg, , , , , , H1_ram_block[10][0]_clock_0, , H1_ram_block[10][0]_clock_enable_0, , , );
H1_ram_block[10][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[10][0]_PORT_A_data_out, H1_ram_block[10][0]_clock_0, , , H1_ram_block[10][0]_clock_enable_0);
H1_ram_block[10][0] = H1_ram_block[10][0]_PORT_A_data_out_reg[0];


--H1_ram_block[8][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][0] at M4K_X15_Y10
H1_ram_block[8][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][0]_PORT_A_address_reg = DFFE(H1_ram_block[8][0]_PORT_A_address, H1_ram_block[8][0]_clock_0, , , H1_ram_block[8][0]_clock_enable_0);
H1_ram_block[8][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[8][0]_clock_enable_0 = VCC;
H1_ram_block[8][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][0]_PORT_A_address_reg, , , , , , H1_ram_block[8][0]_clock_0, , H1_ram_block[8][0]_clock_enable_0, , , );
H1_ram_block[8][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[8][0]_PORT_A_data_out, H1_ram_block[8][0]_clock_0, , , H1_ram_block[8][0]_clock_enable_0);
H1_ram_block[8][0] = H1_ram_block[8][0]_PORT_A_data_out_reg[0];


--K1L11 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~113 at LC_X22_Y31_N6
--operation mode is normal

K1L11 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[10][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[8][0]);


--H1_ram_block[11][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][0] at M4K_X15_Y68
H1_ram_block[11][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][0]_PORT_A_address_reg = DFFE(H1_ram_block[11][0]_PORT_A_address, H1_ram_block[11][0]_clock_0, , , H1_ram_block[11][0]_clock_enable_0);
H1_ram_block[11][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[11][0]_clock_enable_0 = VCC;
H1_ram_block[11][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][0]_PORT_A_address_reg, , , , , , H1_ram_block[11][0]_clock_0, , H1_ram_block[11][0]_clock_enable_0, , , );
H1_ram_block[11][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][0]_PORT_A_data_out, H1_ram_block[11][0]_clock_0, , , H1_ram_block[11][0]_clock_enable_0);
H1_ram_block[11][0] = H1_ram_block[11][0]_PORT_A_data_out_reg[0];


--H1_ram_block[9][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[9][0] at M4K_X15_Y76
H1_ram_block[9][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[9][0]_PORT_A_address_reg = DFFE(H1_ram_block[9][0]_PORT_A_address, H1_ram_block[9][0]_clock_0, , , H1_ram_block[9][0]_clock_enable_0);
H1_ram_block[9][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[9][0]_clock_enable_0 = VCC;
H1_ram_block[9][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[9][0]_PORT_A_address_reg, , , , , , H1_ram_block[9][0]_clock_0, , H1_ram_block[9][0]_clock_enable_0, , , );
H1_ram_block[9][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[9][0]_PORT_A_data_out, H1_ram_block[9][0]_clock_0, , , H1_ram_block[9][0]_clock_enable_0);
H1_ram_block[9][0] = H1_ram_block[9][0]_PORT_A_data_out_reg[0];


--K1L01 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~112 at LC_X22_Y31_N3
--operation mode is normal

K1L01 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[11][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[9][0]);


--K1L31 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~118 at LC_X22_Y31_N5
--operation mode is normal

K1L31 = H1_rdaddress_buffer[1][3] & (H1_rdaddress_buffer[1][2] # K1L01 # K1L11);


--K1L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~41 at LC_X23_Y31_N7
--operation mode is normal

K1L1 = K1L6 # K1L7 & (K1L31 # K1L21);


--K1L491 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result2059w~507 at LC_X30_Y31_N6
--operation mode is normal

H1_rdaddress_buffer[1][2]_qfbk = H1_rdaddress_buffer[1][2];
K1L491 = H1_rdaddress_buffer[1][0] & !H1_rdaddress_buffer[1][2]_qfbk & H1_rdaddress_buffer[1][1];

--H1_rdaddress_buffer[1][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][2] at LC_X30_Y31_N6
--operation mode is normal

H1_rdaddress_buffer[1][2]_sload_eqn = H1_rdaddress_buffer[0][2];
H1_rdaddress_buffer[1][2] = DFFEA(H1_rdaddress_buffer[1][2]_sload_eqn, GLOBAL(g_clk), VCC, , , , );


--H1_ram_block[11][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][1] at M4K_X15_Y3
H1_ram_block[11][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][1]_PORT_A_address_reg = DFFE(H1_ram_block[11][1]_PORT_A_address, H1_ram_block[11][1]_clock_0, , , H1_ram_block[11][1]_clock_enable_0);
H1_ram_block[11][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[11][1]_clock_enable_0 = VCC;
H1_ram_block[11][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][1]_PORT_A_address_reg, , , , , , H1_ram_block[11][1]_clock_0, , H1_ram_block[11][1]_clock_enable_0, , , );
H1_ram_block[11][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][1]_PORT_A_data_out, H1_ram_block[11][1]_clock_0, , , H1_ram_block[11][1]_clock_enable_0);
H1_ram_block[11][1] = H1_ram_block[11][1]_PORT_A_data_out_reg[0];


--H1_ram_block[3][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][1] at M4K_X51_Y5
H1_ram_block[3][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][1]_PORT_A_address_reg = DFFE(H1_ram_block[3][1]_PORT_A_address, H1_ram_block[3][1]_clock_0, , , H1_ram_block[3][1]_clock_enable_0);
H1_ram_block[3][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[3][1]_clock_enable_0 = VCC;
H1_ram_block[3][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][1]_PORT_A_address_reg, , , , , , H1_ram_block[3][1]_clock_0, , H1_ram_block[3][1]_clock_enable_0, , , );
H1_ram_block[3][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][1]_PORT_A_data_out, H1_ram_block[3][1]_clock_0, , , H1_ram_block[3][1]_clock_enable_0);
H1_ram_block[3][1] = H1_ram_block[3][1]_PORT_A_data_out_reg[0];


--K1L32 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~412 at LC_X30_Y31_N7
--operation mode is normal

K1L32 = K1L491 & (H1_rdaddress_buffer[1][3] & H1_ram_block[11][1] # !H1_rdaddress_buffer[1][3] & H1_ram_block[3][1]);


--K1L391 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result2059w~506 at LC_X30_Y31_N4
--operation mode is normal

K1L391 = !H1_rdaddress_buffer[1][2] & !H1_rdaddress_buffer[1][0] & !H1_rdaddress_buffer[1][1];


--H1_ram_block[8][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][1] at M4K_X73_Y45
H1_ram_block[8][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][1]_PORT_A_address_reg = DFFE(H1_ram_block[8][1]_PORT_A_address, H1_ram_block[8][1]_clock_0, , , H1_ram_block[8][1]_clock_enable_0);
H1_ram_block[8][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[8][1]_clock_enable_0 = VCC;
H1_ram_block[8][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][1]_PORT_A_address_reg, , , , , , H1_ram_block[8][1]_clock_0, , H1_ram_block[8][1]_clock_enable_0, , , );
H1_ram_block[8][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[8][1]_PORT_A_data_out, H1_ram_block[8][1]_clock_0, , , H1_ram_block[8][1]_clock_enable_0);
H1_ram_block[8][1] = H1_ram_block[8][1]_PORT_A_data_out_reg[0];


--H1_ram_block[0][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][1] at M4K_X73_Y51
H1_ram_block[0][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][1]_PORT_A_address_reg = DFFE(H1_ram_block[0][1]_PORT_A_address, H1_ram_block[0][1]_clock_0, , , H1_ram_block[0][1]_clock_enable_0);
H1_ram_block[0][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[0][1]_clock_enable_0 = VCC;
H1_ram_block[0][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][1]_PORT_A_address_reg, , , , , , H1_ram_block[0][1]_clock_0, , H1_ram_block[0][1]_clock_enable_0, , , );
H1_ram_block[0][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][1]_PORT_A_data_out, H1_ram_block[0][1]_clock_0, , , H1_ram_block[0][1]_clock_enable_0);
H1_ram_block[0][1] = H1_ram_block[0][1]_PORT_A_data_out_reg[0];


--K1L22 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~411 at LC_X30_Y31_N0
--operation mode is normal

K1L22 = K1L391 & (H1_rdaddress_buffer[1][3] & H1_ram_block[8][1] # !H1_rdaddress_buffer[1][3] & H1_ram_block[0][1]);


--H1_ram_block[14][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[14][1] at M4K_X15_Y21
H1_ram_block[14][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[14][1]_PORT_A_address_reg = DFFE(H1_ram_block[14][1]_PORT_A_address, H1_ram_block[14][1]_clock_0, , , H1_ram_block[14][1]_clock_enable_0);
H1_ram_block[14][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[14][1]_clock_enable_0 = VCC;
H1_ram_block[14][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[14][1]_PORT_A_address_reg, , , , , , H1_ram_block[14][1]_clock_0, , H1_ram_block[14][1]_clock_enable_0, , , );
H1_ram_block[14][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[14][1]_PORT_A_data_out, H1_ram_block[14][1]_clock_0, , , H1_ram_block[14][1]_clock_enable_0);
H1_ram_block[14][1] = H1_ram_block[14][1]_PORT_A_data_out_reg[0];


--H1_ram_block[12][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[12][1] at M4K_X51_Y12
H1_ram_block[12][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[12][1]_PORT_A_address_reg = DFFE(H1_ram_block[12][1]_PORT_A_address, H1_ram_block[12][1]_clock_0, , , H1_ram_block[12][1]_clock_enable_0);
H1_ram_block[12][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[12][1]_clock_enable_0 = VCC;
H1_ram_block[12][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[12][1]_PORT_A_address_reg, , , , , , H1_ram_block[12][1]_clock_0, , H1_ram_block[12][1]_clock_enable_0, , , );
H1_ram_block[12][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[12][1]_PORT_A_data_out, H1_ram_block[12][1]_clock_0, , , H1_ram_block[12][1]_clock_enable_0);
H1_ram_block[12][1] = H1_ram_block[12][1]_PORT_A_data_out_reg[0];


--K1L81 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~403 at LC_X29_Y31_N2
--operation mode is normal

K1L81 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[14][1] # !H1_rdaddress_buffer[1][1] & H1_ram_block[12][1]);


--H1_ram_block[15][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[15][1] at M4K_X51_Y18
H1_ram_block[15][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[15][1]_PORT_A_address_reg = DFFE(H1_ram_block[15][1]_PORT_A_address, H1_ram_block[15][1]_clock_0, , , H1_ram_block[15][1]_clock_enable_0);
H1_ram_block[15][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[15][1]_clock_enable_0 = VCC;
H1_ram_block[15][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[15][1]_PORT_A_address_reg, , , , , , H1_ram_block[15][1]_clock_0, , H1_ram_block[15][1]_clock_enable_0, , , );
H1_ram_block[15][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[15][1]_PORT_A_data_out, H1_ram_block[15][1]_clock_0, , , H1_ram_block[15][1]_clock_enable_0);
H1_ram_block[15][1] = H1_ram_block[15][1]_PORT_A_data_out_reg[0];


--H1_ram_block[13][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[13][1] at M4K_X15_Y45
H1_ram_block[13][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[13][1]_PORT_A_address_reg = DFFE(H1_ram_block[13][1]_PORT_A_address, H1_ram_block[13][1]_clock_0, , , H1_ram_block[13][1]_clock_enable_0);
H1_ram_block[13][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[13][1]_clock_enable_0 = VCC;
H1_ram_block[13][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[13][1]_PORT_A_address_reg, , , , , , H1_ram_block[13][1]_clock_0, , H1_ram_block[13][1]_clock_enable_0, , , );
H1_ram_block[13][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[13][1]_PORT_A_data_out, H1_ram_block[13][1]_clock_0, , , H1_ram_block[13][1]_clock_enable_0);
H1_ram_block[13][1] = H1_ram_block[13][1]_PORT_A_data_out_reg[0];


--K1L91 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~405 at LC_X29_Y31_N1
--operation mode is normal

K1L91 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[15][1] # !H1_rdaddress_buffer[1][1] & H1_ram_block[13][1]);


--K1L02 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~408 at LC_X29_Y31_N3
--operation mode is normal

K1L02 = H1_rdaddress_buffer[1][3] & H1_rdaddress_buffer[1][2] & (K1L91 # K1L81);


--H1_ram_block[5][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[5][1] at M4K_X15_Y27
H1_ram_block[5][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[5][1]_PORT_A_address_reg = DFFE(H1_ram_block[5][1]_PORT_A_address, H1_ram_block[5][1]_clock_0, , , H1_ram_block[5][1]_clock_enable_0);
H1_ram_block[5][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[5][1]_clock_enable_0 = VCC;
H1_ram_block[5][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[5][1]_PORT_A_address_reg, , , , , , H1_ram_block[5][1]_clock_0, , H1_ram_block[5][1]_clock_enable_0, , , );
H1_ram_block[5][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[5][1]_PORT_A_data_out, H1_ram_block[5][1]_clock_0, , , H1_ram_block[5][1]_clock_enable_0);
H1_ram_block[5][1] = H1_ram_block[5][1]_PORT_A_data_out_reg[0];


--H1_ram_block[4][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[4][1] at M4K_X15_Y28
H1_ram_block[4][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[4][1]_PORT_A_address_reg = DFFE(H1_ram_block[4][1]_PORT_A_address, H1_ram_block[4][1]_clock_0, , , H1_ram_block[4][1]_clock_enable_0);
H1_ram_block[4][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[4][1]_clock_enable_0 = VCC;
H1_ram_block[4][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[4][1]_PORT_A_address_reg, , , , , , H1_ram_block[4][1]_clock_0, , H1_ram_block[4][1]_clock_enable_0, , , );
H1_ram_block[4][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[4][1]_PORT_A_data_out, H1_ram_block[4][1]_clock_0, , , H1_ram_block[4][1]_clock_enable_0);
H1_ram_block[4][1] = H1_ram_block[4][1]_PORT_A_data_out_reg[0];


--K1L41 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~258 at LC_X29_Y31_N9
--operation mode is normal