altsyncram.inc

FPGA开发光盘各章节实例的设计工程与源码

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-- altqpram.inc
--
-- Altqpram functions header
--
-- (c) Altera Corporation, 2000
--
-- Version 1.0
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FUNCTION altsyncram	(
						wren_a,
						wren_b,
						data_a[OPERATION_MODE != "ROM" ? WIDTH_A - 1 : 0..0],
						data_b[(OPERATION_MODE == "BIDIR_DUAL_PORT") ? WIDTH_B - 1 : 0..0],
						address_a[WIDTHAD_A - 1..0],
						address_b[(OPERATION_MODE == "BIDIR_DUAL_PORT" # OPERATION_MODE == "DUAL_PORT") ? WIDTHAD_B - 1 : 0..0],
						clock0,
						clock1,
						clocken0,
						clocken1,
						rden_b,
						aclr0,
						aclr1,
						byteena_a[OPERATION_MODE != "ROM" ? ((WIDTH_A > 15) ? ((WIDTH_BYTEENA_A > 1 ? WIDTH_BYTEENA_A-1 : 0)) : 0 ): 0..0],
						byteena_b[OPERATION_MODE == "BIDIR_DUAL_PORT" ? ((WIDTH_B > 15)? (WIDTH_BYTEENA_B > 1 ? WIDTH_BYTEENA_B-1 : 0) : 0 ): 0..0]
					)
					WITH
					(
						OPERATION_MODE,
						WIDTH_A,
						WIDTHAD_A,
						NUMWORDS_A,
						INDATA_ACLR_A,
						WRCONTROL_ACLR_A,
						ADDRESS_ACLR_A,
						WIDTH_B,
						WIDTHAD_B,
						NUMWORDS_B,
						INDATA_REG_B,
						INDATA_ACLR_B,
						WRCONTROL_WRADDRESS_REG_B,
						WRCONTROL_ACLR_B,
						ADDRESS_ACLR_B,
						OUTDATA_REG_A,
						OUTDATA_ACLR_A,
						BYTEENA_ACLR_A,
						RDCONTROL_REG_B,
						RDCONTROL_ACLR_B,
						ADDRESS_REG_B,
						OUTDATA_REG_B,
						OUTDATA_ACLR_B,
						BYTEENA_REG_B,
						BYTEENA_ACLR_B,
						INIT_FILE,
						INIT_FILE_LAYOUT,
						MAXIMUM_DEPTH,
						WIDTH_BYTEENA_A,
						WIDTH_BYTEENA_B,
						BYTE_SIZE,
						READ_DURING_WRITE_MODE_MIXED_PORTS,
						RAM_BLOCK_TYPE,
						DEVICE_FAMILY
					)
					RETURNS
					(
						q_a[WIDTH_A - 1..0],
						q_b[(OPERATION_MODE == "DUAL_PORT" # OPERATION_MODE == "BIDIR_DUAL_PORT") ? WIDTH_B - 1 : 0..0]
					);