filter_con.tdf

FPGA开发光盘各章节实例的设计工程与源码

parameters
(
	x_width = 12
);

constant dff_num = x_width + 6;

subdesign filter_con
(
	clk				: input;
	clr				: input = vcc;
	ad_end  		: input;
	shifter_en		: output;
	ps_load			: output;
	add_load		: output;
	add_sub 		: output;
	flip_en 		: output;
)

variable
shift[dff_num..1] : dffe;
base			  : node;

begin
	shift[].clk = clk;
	shift[].clrn = clr;
	
	shift[1].d = ad_end;
	shift[2].d = shift[1].q;
	base = !shift[1].q&shift[2].q;
	shifter_en = base;
	
	shift[3].d = base;
	for i in 4 to dff_num generate
		shift[i].d = shift[i-1].q;
	end generate;
		ps_load = shift[3].q;
		add_load = shift[6].q;
		add_sub = !shift[6+x_width-1].q;
		flip_en = shift[6+x_width].q;
end;