filter.fit.summary

FPGA开发光盘各章节实例的设计工程与源码

Fitter Status : Successful - Mon Dec 10 15:46:00 2007
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : filter
Top-level Entity Name : filter
Family : Stratix
Device : EP1S80F1508C7
Timing Models : Final
Total logic elements : 651 / 79,040 ( < 1 % )
Total pins : 49 / 1,212 ( 4 % )
Total virtual pins : 0
Total memory bits : 1,048,576 / 7,427,520 ( 14 % )
DSP block 9-bit elements : 0 / 176 ( 0 % )
Total PLLs : 0 / 12 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )