filter.map.eqn

FPGA开发光盘各章节实例的设计工程与源码

--H1_ram_block[3][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][1]
H1_ram_block[3][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][1]_PORT_A_address_reg = DFFE(H1_ram_block[3][1]_PORT_A_address, H1_ram_block[3][1]_clock_0, , , H1_ram_block[3][1]_clock_enable_0);
H1_ram_block[3][1]_clock_0 = g_clk;
H1_ram_block[3][1]_clock_enable_0 = VCC;
H1_ram_block[3][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][1]_PORT_A_address_reg, , , , , , H1_ram_block[3][1]_clock_0, , H1_ram_block[3][1]_clock_enable_0, , , );
H1_ram_block[3][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][1]_PORT_A_data_out, H1_ram_block[3][1]_clock_0, , , H1_ram_block[3][1]_clock_enable_0);
H1_ram_block[3][1] = H1_ram_block[3][1]_PORT_A_data_out_reg[0];


--K1L32 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~412
--operation mode is normal

K1L32 = K1L491 & (H1_rdaddress_buffer[1][3] & H1_ram_block[11][1] # !H1_rdaddress_buffer[1][3] & H1_ram_block[3][1]);


--K1L391 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result2059w~506
--operation mode is normal

K1L391 = !H1_rdaddress_buffer[1][0] & !H1_rdaddress_buffer[1][1] & !H1_rdaddress_buffer[1][2];


--H1_ram_block[8][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][1]
H1_ram_block[8][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][1]_PORT_A_address_reg = DFFE(H1_ram_block[8][1]_PORT_A_address, H1_ram_block[8][1]_clock_0, , , H1_ram_block[8][1]_clock_enable_0);
H1_ram_block[8][1]_clock_0 = g_clk;
H1_ram_block[8][1]_clock_enable_0 = VCC;
H1_ram_block[8][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][1]_PORT_A_address_reg, , , , , , H1_ram_block[8][1]_clock_0, , H1_ram_block[8][1]_clock_enable_0, , , );
H1_ram_block[8][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[8][1]_PORT_A_data_out, H1_ram_block[8][1]_clock_0, , , H1_ram_block[8][1]_clock_enable_0);
H1_ram_block[8][1] = H1_ram_block[8][1]_PORT_A_data_out_reg[0];


--H1_ram_block[0][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][1]
H1_ram_block[0][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][1]_PORT_A_address_reg = DFFE(H1_ram_block[0][1]_PORT_A_address, H1_ram_block[0][1]_clock_0, , , H1_ram_block[0][1]_clock_enable_0);
H1_ram_block[0][1]_clock_0 = g_clk;
H1_ram_block[0][1]_clock_enable_0 = VCC;
H1_ram_block[0][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][1]_PORT_A_address_reg, , , , , , H1_ram_block[0][1]_clock_0, , H1_ram_block[0][1]_clock_enable_0, , , );
H1_ram_block[0][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][1]_PORT_A_data_out, H1_ram_block[0][1]_clock_0, , , H1_ram_block[0][1]_clock_enable_0);
H1_ram_block[0][1] = H1_ram_block[0][1]_PORT_A_data_out_reg[0];


--K1L22 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~411
--operation mode is normal

K1L22 = K1L391 & (H1_rdaddress_buffer[1][3] & H1_ram_block[8][1] # !H1_rdaddress_buffer[1][3] & H1_ram_block[0][1]);


--H1_ram_block[14][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[14][1]
H1_ram_block[14][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[14][1]_PORT_A_address_reg = DFFE(H1_ram_block[14][1]_PORT_A_address, H1_ram_block[14][1]_clock_0, , , H1_ram_block[14][1]_clock_enable_0);
H1_ram_block[14][1]_clock_0 = g_clk;
H1_ram_block[14][1]_clock_enable_0 = VCC;
H1_ram_block[14][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[14][1]_PORT_A_address_reg, , , , , , H1_ram_block[14][1]_clock_0, , H1_ram_block[14][1]_clock_enable_0, , , );
H1_ram_block[14][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[14][1]_PORT_A_data_out, H1_ram_block[14][1]_clock_0, , , H1_ram_block[14][1]_clock_enable_0);
H1_ram_block[14][1] = H1_ram_block[14][1]_PORT_A_data_out_reg[0];


--H1_ram_block[12][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[12][1]
H1_ram_block[12][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[12][1]_PORT_A_address_reg = DFFE(H1_ram_block[12][1]_PORT_A_address, H1_ram_block[12][1]_clock_0, , , H1_ram_block[12][1]_clock_enable_0);
H1_ram_block[12][1]_clock_0 = g_clk;
H1_ram_block[12][1]_clock_enable_0 = VCC;
H1_ram_block[12][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[12][1]_PORT_A_address_reg, , , , , , H1_ram_block[12][1]_clock_0, , H1_ram_block[12][1]_clock_enable_0, , , );
H1_ram_block[12][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[12][1]_PORT_A_data_out, H1_ram_block[12][1]_clock_0, , , H1_ram_block[12][1]_clock_enable_0);
H1_ram_block[12][1] = H1_ram_block[12][1]_PORT_A_data_out_reg[0];


--K1L81 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~403
--operation mode is normal

K1L81 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[14][1] # !H1_rdaddress_buffer[1][1] & H1_ram_block[12][1]);


--H1_ram_block[15][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[15][1]
H1_ram_block[15][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[15][1]_PORT_A_address_reg = DFFE(H1_ram_block[15][1]_PORT_A_address, H1_ram_block[15][1]_clock_0, , , H1_ram_block[15][1]_clock_enable_0);
H1_ram_block[15][1]_clock_0 = g_clk;
H1_ram_block[15][1]_clock_enable_0 = VCC;
H1_ram_block[15][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[15][1]_PORT_A_address_reg, , , , , , H1_ram_block[15][1]_clock_0, , H1_ram_block[15][1]_clock_enable_0, , , );
H1_ram_block[15][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[15][1]_PORT_A_data_out, H1_ram_block[15][1]_clock_0, , , H1_ram_block[15][1]_clock_enable_0);
H1_ram_block[15][1] = H1_ram_block[15][1]_PORT_A_data_out_reg[0];


--H1_ram_block[13][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[13][1]
H1_ram_block[13][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[13][1]_PORT_A_address_reg = DFFE(H1_ram_block[13][1]_PORT_A_address, H1_ram_block[13][1]_clock_0, , , H1_ram_block[13][1]_clock_enable_0);
H1_ram_block[13][1]_clock_0 = g_clk;
H1_ram_block[13][1]_clock_enable_0 = VCC;
H1_ram_block[13][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[13][1]_PORT_A_address_reg, , , , , , H1_ram_block[13][1]_clock_0, , H1_ram_block[13][1]_clock_enable_0, , , );
H1_ram_block[13][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[13][1]_PORT_A_data_out, H1_ram_block[13][1]_clock_0, , , H1_ram_block[13][1]_clock_enable_0);
H1_ram_block[13][1] = H1_ram_block[13][1]_PORT_A_data_out_reg[0];


--K1L91 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~405
--operation mode is normal

K1L91 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[15][1] # !H1_rdaddress_buffer[1][1] & H1_ram_block[13][1]);


--K1L02 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~408
--operation mode is normal

K1L02 = H1_rdaddress_buffer[1][2] & H1_rdaddress_buffer[1][3] & (K1L81 # K1L91);


--H1_ram_block[5][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[5][1]
H1_ram_block[5][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[5][1]_PORT_A_address_reg = DFFE(H1_ram_block[5][1]_PORT_A_address, H1_ram_block[5][1]_clock_0, , , H1_ram_block[5][1]_clock_enable_0);
H1_ram_block[5][1]_clock_0 = g_clk;
H1_ram_block[5][1]_clock_enable_0 = VCC;
H1_ram_block[5][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[5][1]_PORT_A_address_reg, , , , , , H1_ram_block[5][1]_clock_0, , H1_ram_block[5][1]_clock_enable_0, , , );
H1_ram_block[5][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[5][1]_PORT_A_data_out, H1_ram_block[5][1]_clock_0, , , H1_ram_block[5][1]_clock_enable_0);
H1_ram_block[5][1] = H1_ram_block[5][1]_PORT_A_data_out_reg[0];


--H1_ram_block[4][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[4][1]
H1_ram_block[4][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[4][1]_PORT_A_address_reg = DFFE(H1_ram_block[4][1]_PORT_A_address, H1_ram_block[4][1]_clock_0, , , H1_ram_block[4][1]_clock_enable_0);
H1_ram_block[4][1]_clock_0 = g_clk;
H1_ram_block[4][1]_clock_enable_0 = VCC;
H1_ram_block[4][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[4][1]_PORT_A_address_reg, , , , , , H1_ram_block[4][1]_clock_0, , H1_ram_block[4][1]_clock_enable_0, , , );
H1_ram_block[4][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[4][1]_PORT_A_data_out, H1_ram_block[4][1]_clock_0, , , H1_ram_block[4][1]_clock_enable_0);
H1_ram_block[4][1] = H1_ram_block[4][1]_PORT_A_data_out_reg[0];


--K1L41 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~258
--operation mode is normal

K1L41 = !H1_rdaddress_buffer[1][1] & (H1_rdaddress_buffer[1][0] & H1_ram_block[5][1] # !H1_rdaddress_buffer[1][0] & H1_ram_block[4][1]);


--H1_ram_block[7][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[7][1]
H1_ram_block[7][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[7][1]_PORT_A_address_reg = DFFE(H1_ram_block[7][1]_PORT_A_address, H1_ram_block[7][1]_clock_0, , , H1_ram_block[7][1]_clock_enable_0);
H1_ram_block[7][1]_clock_0 = g_clk;
H1_ram_block[7][1]_clock_enable_0 = VCC;
H1_ram_block[7][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[7][1]_PORT_A_address_reg, , , , , , H1_ram_block[7][1]_clock_0, , H1_ram_block[7][1]_clock_enable_0, , , );
H1_ram_block[7][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[7][1]_PORT_A_data_out, H1_ram_block[7][1]_clock_0, , , H1_ram_block[7][1]_clock_enable_0);
H1_ram_block[7][1] = H1_ram_block[7][1]_PORT_A_data_out_reg[0];


--H1_ram_block[6][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[6][1]
H1_ram_block[6][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[6][1]_PORT_A_address_reg = DFFE(H1_ram_block[6][1]_PORT_A_address, H1_ram_block[6][1]_clock_0, , , H1_ram_block[6][1]_clock_enable_0);
H1_ram_block[6][1]_clock_0 = g_clk;
H1_ram_block[6][1]_clock_enable_0 = VCC;
H1_ram_block[6][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[6][1]_PORT_A_address_reg, , , , , , H1_ram_block[6][1]_clock_0, , H1_ram_block[6][1]_clock_enable_0, , , );
H1_ram_block[6][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[6][1]_PORT_A_data_out, H1_ram_block[6][1]_clock_0, , , H1_ram_block[6][1]_clock_enable_0);
H1_ram_block[6][1] = H1_ram_block[6][1]_PORT_A_data_out_reg[0];


--K1L51 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~259
--operation mode is normal

K1L51 = H1_rdaddress_buffer[1][1] & (H1_rdaddress_buffer[1][0] & H1_ram_block[7][1] # !H1_rdaddress_buffer[1][0] & H1_ram_block[6][1]);


--K1L61 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~263
--operation mode is normal

K1L61 = H1_rdaddress_buffer[1][2] & !H1_rdaddress_buffer[1][3] & (K1L41 # K1L51);


--K1L591 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result2059w~508
--operation mode is normal

K1L591 = H1_rdaddress_buffer[1][1] & !H1_rdaddress_buffer[1][0] & !H1_rdaddress_buffer[1][2];


--H1_ram_block[10][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[10][1]
H1_ram_block[10][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[10][1]_PORT_A_address_reg = DFFE(H1_ram_block[10][1]_PORT_A_address, H1_ram_block[10][1]_clock_0, , , H1_ram_block[10][1]_clock_enable_0);
H1_ram_block[10][1]_clock_0 = g_clk;
H1_ram_block[10][1]_clock_enable_0 = VCC;
H1_ram_block[10][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[10][1]_PORT_A_address_reg, , , , , , H1_ram_block[10][1]_clock_0, , H1_ram_block[10][1]_clock_enable_0, , , );
H1_ram_block[10][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[10][1]_PORT_A_data_out, H1_ram_block[10][1]_clock_0, , , H1_ram_block[10][1]_clock_enable_0);
H1_ram_block[10][1] = H1_ram_block[10][1]_PORT_A_data_out_reg[0];


--H1_ram_block[2][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[2][1]
H1_ram_block[2][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[2][1]_PORT_A_address_reg = DFFE(H1_ram_block[2][1]_PORT_A_address, H1_ram_block[2][1]_clock_0, , , H1_ram_block[2][1]_clock_enable_0);
H1_ram_block[2][1]_clock_0 = g_clk;
H1_ram_block[2][1]_clock_enable_0 = VCC;
H1_ram_block[2][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[2][1]_PORT_A_address_reg, , , , , , H1_ram_block[2][1]_clock_0, , H1_ram_block[2][1]_clock_enable_0, , , );
H1_ram_block[2][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[2][1]_PORT_A_data_out, H1_ram_block[2][1]_clock_0, , , H1_ram_block[2][1]_clock_enable_0);
H1_ram_block[2][1] = H1_ram_block[2][1]_PORT_A_data_out_reg[0];


--K1L12 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~410
--operation mode is normal

K1L12 = K1L591 & (H1_rdaddress_buffer[1][3] & H1_ram_block[10][1] # !H1_rdaddress_buffer[1][3] & H1_ram_block[2][1]);


--K1L291 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result2059w~505
--operation mode is normal

K1L291 = H1_rdaddress_buffer[1][0] & !H1_rdaddress_buffer[1][1] & !H1_rdaddress_buffer[1][2];


--H1_ram_block[9][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[9][1]
H1_ram_block[9][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[9][1]_PORT_A_address_reg = DFFE(H1_ram_block[9][1]_PORT_A_address, H1_ram_block[9][1]_clock_0, , , H1_ram_block[9][1]_clock_enable_0);
H1_ram_block[9][1]_clock_0 = g_clk;
H1_ram_block[9][1]_clock_enable_0 = VCC;
H1_ram_block[9][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[9][1]_PORT_A_address_reg, , , , , , H1_ram_block[9][1]_clock_0, , H1_ram_block[9][1]_clock_enable_0, , , );
H1_ram_block[9][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[9][1]_PORT_A_data_out, H1_ram_block[9][1]_clock_0, , , H1_ram_block[9][1]_clock_enable_0);
H1_ram_block[9][1] = H1_ram_block[9][1]_PORT_A_data_out_reg[0];