filter.map.eqn

FPGA开发光盘各章节实例的设计工程与源码

--operation mode is normal

K1L5 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[6][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[4][0]);


--H1_rdaddress_buffer[1][3] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][3]
--operation mode is normal

H1_rdaddress_buffer[1][3]_lut_out = H1_rdaddress_buffer[0][3];
H1_rdaddress_buffer[1][3] = DFFEA(H1_rdaddress_buffer[1][3]_lut_out, g_clk, VCC, , , , );


--K1L6 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~267
--operation mode is normal

K1L6 = H1_rdaddress_buffer[1][2] & !H1_rdaddress_buffer[1][3] & (K1L4 # K1L5);


--H1_ram_block[15][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[15][0]
H1_ram_block[15][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[15][0]_PORT_A_address_reg = DFFE(H1_ram_block[15][0]_PORT_A_address, H1_ram_block[15][0]_clock_0, , , H1_ram_block[15][0]_clock_enable_0);
H1_ram_block[15][0]_clock_0 = g_clk;
H1_ram_block[15][0]_clock_enable_0 = VCC;
H1_ram_block[15][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[15][0]_PORT_A_address_reg, , , , , , H1_ram_block[15][0]_clock_0, , H1_ram_block[15][0]_clock_enable_0, , , );
H1_ram_block[15][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[15][0]_PORT_A_data_out, H1_ram_block[15][0]_clock_0, , , H1_ram_block[15][0]_clock_enable_0);
H1_ram_block[15][0] = H1_ram_block[15][0]_PORT_A_data_out_reg[0];


--H1_ram_block[13][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[13][0]
H1_ram_block[13][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[13][0]_PORT_A_address_reg = DFFE(H1_ram_block[13][0]_PORT_A_address, H1_ram_block[13][0]_clock_0, , , H1_ram_block[13][0]_clock_enable_0);
H1_ram_block[13][0]_clock_0 = g_clk;
H1_ram_block[13][0]_clock_enable_0 = VCC;
H1_ram_block[13][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[13][0]_PORT_A_address_reg, , , , , , H1_ram_block[13][0]_clock_0, , H1_ram_block[13][0]_clock_enable_0, , , );
H1_ram_block[13][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[13][0]_PORT_A_data_out, H1_ram_block[13][0]_clock_0, , , H1_ram_block[13][0]_clock_enable_0);
H1_ram_block[13][0] = H1_ram_block[13][0]_PORT_A_data_out_reg[0];


--K1L2 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~56
--operation mode is normal

K1L2 = H1_ram_block[15][0] & (H1_ram_block[13][0] # H1_rdaddress_buffer[1][1]) # !H1_ram_block[15][0] & H1_ram_block[13][0] & !H1_rdaddress_buffer[1][1];


--H1_ram_block[14][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[14][0]
H1_ram_block[14][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[14][0]_PORT_A_address_reg = DFFE(H1_ram_block[14][0]_PORT_A_address, H1_ram_block[14][0]_clock_0, , , H1_ram_block[14][0]_clock_enable_0);
H1_ram_block[14][0]_clock_0 = g_clk;
H1_ram_block[14][0]_clock_enable_0 = VCC;
H1_ram_block[14][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[14][0]_PORT_A_address_reg, , , , , , H1_ram_block[14][0]_clock_0, , H1_ram_block[14][0]_clock_enable_0, , , );
H1_ram_block[14][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[14][0]_PORT_A_data_out, H1_ram_block[14][0]_clock_0, , , H1_ram_block[14][0]_clock_enable_0);
H1_ram_block[14][0] = H1_ram_block[14][0]_PORT_A_data_out_reg[0];


--H1_ram_block[12][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[12][0]
H1_ram_block[12][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[12][0]_PORT_A_address_reg = DFFE(H1_ram_block[12][0]_PORT_A_address, H1_ram_block[12][0]_clock_0, , , H1_ram_block[12][0]_clock_enable_0);
H1_ram_block[12][0]_clock_0 = g_clk;
H1_ram_block[12][0]_clock_enable_0 = VCC;
H1_ram_block[12][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[12][0]_PORT_A_address_reg, , , , , , H1_ram_block[12][0]_clock_0, , H1_ram_block[12][0]_clock_enable_0, , , );
H1_ram_block[12][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[12][0]_PORT_A_data_out, H1_ram_block[12][0]_clock_0, , , H1_ram_block[12][0]_clock_enable_0);
H1_ram_block[12][0] = H1_ram_block[12][0]_PORT_A_data_out_reg[0];


--K1L3 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~61
--operation mode is normal

K1L3 = H1_ram_block[14][0] & (H1_ram_block[12][0] # H1_rdaddress_buffer[1][1]) # !H1_ram_block[14][0] & H1_ram_block[12][0] & !H1_rdaddress_buffer[1][1];


--K1L7 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~528
--operation mode is normal

K1L7 = H1_rdaddress_buffer[1][0] & K1L2 # !H1_rdaddress_buffer[1][0] & K1L3 # !H1_rdaddress_buffer[1][2];


--H1_ram_block[3][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][0]
H1_ram_block[3][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][0]_PORT_A_address_reg = DFFE(H1_ram_block[3][0]_PORT_A_address, H1_ram_block[3][0]_clock_0, , , H1_ram_block[3][0]_clock_enable_0);
H1_ram_block[3][0]_clock_0 = g_clk;
H1_ram_block[3][0]_clock_enable_0 = VCC;
H1_ram_block[3][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][0]_PORT_A_address_reg, , , , , , H1_ram_block[3][0]_clock_0, , H1_ram_block[3][0]_clock_enable_0, , , );
H1_ram_block[3][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][0]_PORT_A_data_out, H1_ram_block[3][0]_clock_0, , , H1_ram_block[3][0]_clock_enable_0);
H1_ram_block[3][0] = H1_ram_block[3][0]_PORT_A_data_out_reg[0];


--H1_ram_block[1][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[1][0]
H1_ram_block[1][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[1][0]_PORT_A_address_reg = DFFE(H1_ram_block[1][0]_PORT_A_address, H1_ram_block[1][0]_clock_0, , , H1_ram_block[1][0]_clock_enable_0);
H1_ram_block[1][0]_clock_0 = g_clk;
H1_ram_block[1][0]_clock_enable_0 = VCC;
H1_ram_block[1][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[1][0]_PORT_A_address_reg, , , , , , H1_ram_block[1][0]_clock_0, , H1_ram_block[1][0]_clock_enable_0, , , );
H1_ram_block[1][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[1][0]_PORT_A_data_out, H1_ram_block[1][0]_clock_0, , , H1_ram_block[1][0]_clock_enable_0);
H1_ram_block[1][0] = H1_ram_block[1][0]_PORT_A_data_out_reg[0];


--K1L8 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~96
--operation mode is normal

K1L8 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[3][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[1][0]);


--H1_ram_block[2][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[2][0]
H1_ram_block[2][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[2][0]_PORT_A_address_reg = DFFE(H1_ram_block[2][0]_PORT_A_address, H1_ram_block[2][0]_clock_0, , , H1_ram_block[2][0]_clock_enable_0);
H1_ram_block[2][0]_clock_0 = g_clk;
H1_ram_block[2][0]_clock_enable_0 = VCC;
H1_ram_block[2][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[2][0]_PORT_A_address_reg, , , , , , H1_ram_block[2][0]_clock_0, , H1_ram_block[2][0]_clock_enable_0, , , );
H1_ram_block[2][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[2][0]_PORT_A_data_out, H1_ram_block[2][0]_clock_0, , , H1_ram_block[2][0]_clock_enable_0);
H1_ram_block[2][0] = H1_ram_block[2][0]_PORT_A_data_out_reg[0];


--H1_ram_block[0][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][0]
H1_ram_block[0][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][0]_PORT_A_address_reg = DFFE(H1_ram_block[0][0]_PORT_A_address, H1_ram_block[0][0]_clock_0, , , H1_ram_block[0][0]_clock_enable_0);
H1_ram_block[0][0]_clock_0 = g_clk;
H1_ram_block[0][0]_clock_enable_0 = VCC;
H1_ram_block[0][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][0]_PORT_A_address_reg, , , , , , H1_ram_block[0][0]_clock_0, , H1_ram_block[0][0]_clock_enable_0, , , );
H1_ram_block[0][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][0]_PORT_A_data_out, H1_ram_block[0][0]_clock_0, , , H1_ram_block[0][0]_clock_enable_0);
H1_ram_block[0][0] = H1_ram_block[0][0]_PORT_A_data_out_reg[0];


--K1L9 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~97
--operation mode is normal

K1L9 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[2][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[0][0]);


--K1L21 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~117
--operation mode is normal

K1L21 = !H1_rdaddress_buffer[1][2] & !H1_rdaddress_buffer[1][3] & (K1L8 # K1L9);


--H1_ram_block[10][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[10][0]
H1_ram_block[10][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[10][0]_PORT_A_address_reg = DFFE(H1_ram_block[10][0]_PORT_A_address, H1_ram_block[10][0]_clock_0, , , H1_ram_block[10][0]_clock_enable_0);
H1_ram_block[10][0]_clock_0 = g_clk;
H1_ram_block[10][0]_clock_enable_0 = VCC;
H1_ram_block[10][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[10][0]_PORT_A_address_reg, , , , , , H1_ram_block[10][0]_clock_0, , H1_ram_block[10][0]_clock_enable_0, , , );
H1_ram_block[10][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[10][0]_PORT_A_data_out, H1_ram_block[10][0]_clock_0, , , H1_ram_block[10][0]_clock_enable_0);
H1_ram_block[10][0] = H1_ram_block[10][0]_PORT_A_data_out_reg[0];


--H1_ram_block[8][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][0]
H1_ram_block[8][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][0]_PORT_A_address_reg = DFFE(H1_ram_block[8][0]_PORT_A_address, H1_ram_block[8][0]_clock_0, , , H1_ram_block[8][0]_clock_enable_0);
H1_ram_block[8][0]_clock_0 = g_clk;
H1_ram_block[8][0]_clock_enable_0 = VCC;
H1_ram_block[8][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][0]_PORT_A_address_reg, , , , , , H1_ram_block[8][0]_clock_0, , H1_ram_block[8][0]_clock_enable_0, , , );
H1_ram_block[8][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[8][0]_PORT_A_data_out, H1_ram_block[8][0]_clock_0, , , H1_ram_block[8][0]_clock_enable_0);
H1_ram_block[8][0] = H1_ram_block[8][0]_PORT_A_data_out_reg[0];


--K1L11 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~113
--operation mode is normal

K1L11 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[10][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[8][0]);


--H1_ram_block[11][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][0]
H1_ram_block[11][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][0]_PORT_A_address_reg = DFFE(H1_ram_block[11][0]_PORT_A_address, H1_ram_block[11][0]_clock_0, , , H1_ram_block[11][0]_clock_enable_0);
H1_ram_block[11][0]_clock_0 = g_clk;
H1_ram_block[11][0]_clock_enable_0 = VCC;
H1_ram_block[11][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][0]_PORT_A_address_reg, , , , , , H1_ram_block[11][0]_clock_0, , H1_ram_block[11][0]_clock_enable_0, , , );
H1_ram_block[11][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][0]_PORT_A_data_out, H1_ram_block[11][0]_clock_0, , , H1_ram_block[11][0]_clock_enable_0);
H1_ram_block[11][0] = H1_ram_block[11][0]_PORT_A_data_out_reg[0];


--H1_ram_block[9][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[9][0]
H1_ram_block[9][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[9][0]_PORT_A_address_reg = DFFE(H1_ram_block[9][0]_PORT_A_address, H1_ram_block[9][0]_clock_0, , , H1_ram_block[9][0]_clock_enable_0);
H1_ram_block[9][0]_clock_0 = g_clk;
H1_ram_block[9][0]_clock_enable_0 = VCC;
H1_ram_block[9][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[9][0]_PORT_A_address_reg, , , , , , H1_ram_block[9][0]_clock_0, , H1_ram_block[9][0]_clock_enable_0, , , );
H1_ram_block[9][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[9][0]_PORT_A_data_out, H1_ram_block[9][0]_clock_0, , , H1_ram_block[9][0]_clock_enable_0);
H1_ram_block[9][0] = H1_ram_block[9][0]_PORT_A_data_out_reg[0];


--K1L01 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~112
--operation mode is normal

K1L01 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[11][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[9][0]);


--K1L31 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~118
--operation mode is normal

K1L31 = H1_rdaddress_buffer[1][3] & (K1L11 # H1_rdaddress_buffer[1][2] # K1L01);


--K1L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~41
--operation mode is normal

K1L1 = K1L6 # K1L7 & (K1L21 # K1L31);


--K1L491 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result2059w~507
--operation mode is normal

K1L491 = H1_rdaddress_buffer[1][0] & H1_rdaddress_buffer[1][1] & !H1_rdaddress_buffer[1][2];


--H1_ram_block[11][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][1]
H1_ram_block[11][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][1]_PORT_A_address_reg = DFFE(H1_ram_block[11][1]_PORT_A_address, H1_ram_block[11][1]_clock_0, , , H1_ram_block[11][1]_clock_enable_0);
H1_ram_block[11][1]_clock_0 = g_clk;
H1_ram_block[11][1]_clock_enable_0 = VCC;
H1_ram_block[11][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][1]_PORT_A_address_reg, , , , , , H1_ram_block[11][1]_clock_0, , H1_ram_block[11][1]_clock_enable_0, , , );
H1_ram_block[11][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][1]_PORT_A_data_out, H1_ram_block[11][1]_clock_0, , , H1_ram_block[11][1]_clock_enable_0);
H1_ram_block[11][1] = H1_ram_block[11][1]_PORT_A_data_out_reg[0];