filter.map.eqn

FPGA开发光盘各章节实例的设计工程与源码

add_sub_cell[1]_dataa = K1L42 $ B1_shift[17];
M1L5 = CARRY(add_sub_cell[1]_dataa & !E1_accum[4] & !M1L3 # !add_sub_cell[1]_dataa & (!M1L3 # !E1_accum[4]));


--M1_result[0] is accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic

add_sub_cell[0]_dataa = K1L1 $ B1_shift[17];
M1_result[0]_carry_eqn = B1_shift[17];
M1_result[0] = add_sub_cell[0]_dataa $ E1_accum[3] $ M1_result[0]_carry_eqn;

--M1L3 is accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic

add_sub_cell[0]_dataa = K1L1 $ B1_shift[17];
M1L3 = CARRY(add_sub_cell[0]_dataa & (E1_accum[3] # B1_shift[17]) # !add_sub_cell[0]_dataa & E1_accum[3] & B1_shift[17]);


--E1_flip[1] is accumulator:shift_add|flip[1]
--operation mode is normal

E1_flip[1]_lut_out = E1_accum[1];
E1_flip[1] = DFFEA(E1_flip[1]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[2] is accumulator:shift_add|flip[2]
--operation mode is normal

E1_flip[2]_lut_out = E1_accum[2];
E1_flip[2] = DFFEA(E1_flip[2]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[3] is accumulator:shift_add|flip[3]
--operation mode is normal

E1_flip[3]_lut_out = E1_accum[3];
E1_flip[3] = DFFEA(E1_flip[3]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[4] is accumulator:shift_add|flip[4]
--operation mode is normal

E1_flip[4]_lut_out = E1_accum[4];
E1_flip[4] = DFFEA(E1_flip[4]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[5] is accumulator:shift_add|flip[5]
--operation mode is normal

E1_flip[5]_lut_out = E1_accum[5];
E1_flip[5] = DFFEA(E1_flip[5]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[6] is accumulator:shift_add|flip[6]
--operation mode is normal

E1_flip[6]_lut_out = E1_accum[6];
E1_flip[6] = DFFEA(E1_flip[6]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[7] is accumulator:shift_add|flip[7]
--operation mode is normal

E1_flip[7]_lut_out = E1_accum[7];
E1_flip[7] = DFFEA(E1_flip[7]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[8] is accumulator:shift_add|flip[8]
--operation mode is normal

E1_flip[8]_lut_out = E1_accum[8];
E1_flip[8] = DFFEA(E1_flip[8]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[9] is accumulator:shift_add|flip[9]
--operation mode is normal

E1_flip[9]_lut_out = E1_accum[9];
E1_flip[9] = DFFEA(E1_flip[9]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[10] is accumulator:shift_add|flip[10]
--operation mode is normal

E1_flip[10]_lut_out = E1_accum[10];
E1_flip[10] = DFFEA(E1_flip[10]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[11] is accumulator:shift_add|flip[11]
--operation mode is normal

E1_flip[11]_lut_out = E1_accum[11];
E1_flip[11] = DFFEA(E1_flip[11]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[12] is accumulator:shift_add|flip[12]
--operation mode is normal

E1_flip[12]_lut_out = E1_accum[12];
E1_flip[12] = DFFEA(E1_flip[12]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[13] is accumulator:shift_add|flip[13]
--operation mode is normal

E1_flip[13]_lut_out = E1_accum[13];
E1_flip[13] = DFFEA(E1_flip[13]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[14] is accumulator:shift_add|flip[14]
--operation mode is normal

E1_flip[14]_lut_out = E1_accum[14];
E1_flip[14] = DFFEA(E1_flip[14]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[15] is accumulator:shift_add|flip[15]
--operation mode is normal

E1_flip[15]_lut_out = E1_accum[15];
E1_flip[15] = DFFEA(E1_flip[15]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[16] is accumulator:shift_add|flip[16]
--operation mode is normal

E1_flip[16]_lut_out = E1_accum[16];
E1_flip[16] = DFFEA(E1_flip[16]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[17] is accumulator:shift_add|flip[17]
--operation mode is normal

E1_flip[17]_lut_out = E1_accum[17];
E1_flip[17] = DFFEA(E1_flip[17]_lut_out, g_clk, clr, , B1_shift[18], , );


--E1_flip[18] is accumulator:shift_add|flip[18]
--operation mode is normal

E1_flip[18]_lut_out = E1_accum[18];
E1_flip[18] = DFFEA(E1_flip[18]_lut_out, g_clk, clr, , B1_shift[18], , );


--H1_rdaddress_buffer[1][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][2]
--operation mode is normal

H1_rdaddress_buffer[1][2]_lut_out = H1_rdaddress_buffer[0][2];
H1_rdaddress_buffer[1][2] = DFFEA(H1_rdaddress_buffer[1][2]_lut_out, g_clk, VCC, , , , );


--H1_rdaddress_buffer[1][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][0]
--operation mode is normal

H1_rdaddress_buffer[1][0]_lut_out = H1_rdaddress_buffer[0][0];
H1_rdaddress_buffer[1][0] = DFFEA(H1_rdaddress_buffer[1][0]_lut_out, g_clk, VCC, , , , );


--H1_ram_block[7][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[7][0]
H1_ram_block[7][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[7][0]_PORT_A_address_reg = DFFE(H1_ram_block[7][0]_PORT_A_address, H1_ram_block[7][0]_clock_0, , , H1_ram_block[7][0]_clock_enable_0);
H1_ram_block[7][0]_clock_0 = g_clk;
H1_ram_block[7][0]_clock_enable_0 = VCC;
H1_ram_block[7][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[7][0]_PORT_A_address_reg, , , , , , H1_ram_block[7][0]_clock_0, , H1_ram_block[7][0]_clock_enable_0, , , );
H1_ram_block[7][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[7][0]_PORT_A_data_out, H1_ram_block[7][0]_clock_0, , , H1_ram_block[7][0]_clock_enable_0);
H1_ram_block[7][0] = H1_ram_block[7][0]_PORT_A_data_out_reg[0];


--H1_ram_block[5][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[5][0]
H1_ram_block[5][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[5][0]_PORT_A_address_reg = DFFE(H1_ram_block[5][0]_PORT_A_address, H1_ram_block[5][0]_clock_0, , , H1_ram_block[5][0]_clock_enable_0);
H1_ram_block[5][0]_clock_0 = g_clk;
H1_ram_block[5][0]_clock_enable_0 = VCC;
H1_ram_block[5][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[5][0]_PORT_A_address_reg, , , , , , H1_ram_block[5][0]_clock_0, , H1_ram_block[5][0]_clock_enable_0, , , );
H1_ram_block[5][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[5][0]_PORT_A_data_out, H1_ram_block[5][0]_clock_0, , , H1_ram_block[5][0]_clock_enable_0);
H1_ram_block[5][0] = H1_ram_block[5][0]_PORT_A_data_out_reg[0];


--H1_rdaddress_buffer[1][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][1]
--operation mode is normal

H1_rdaddress_buffer[1][1]_lut_out = H1_rdaddress_buffer[0][1];
H1_rdaddress_buffer[1][1] = DFFEA(H1_rdaddress_buffer[1][1]_lut_out, g_clk, VCC, , , , );


--K1L4 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~262
--operation mode is normal

K1L4 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[7][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[5][0]);


--H1_ram_block[6][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[6][0]
H1_ram_block[6][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[6][0]_PORT_A_address_reg = DFFE(H1_ram_block[6][0]_PORT_A_address, H1_ram_block[6][0]_clock_0, , , H1_ram_block[6][0]_clock_enable_0);
H1_ram_block[6][0]_clock_0 = g_clk;
H1_ram_block[6][0]_clock_enable_0 = VCC;
H1_ram_block[6][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[6][0]_PORT_A_address_reg, , , , , , H1_ram_block[6][0]_clock_0, , H1_ram_block[6][0]_clock_enable_0, , , );
H1_ram_block[6][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[6][0]_PORT_A_data_out, H1_ram_block[6][0]_clock_0, , , H1_ram_block[6][0]_clock_enable_0);
H1_ram_block[6][0] = H1_ram_block[6][0]_PORT_A_data_out_reg[0];


--H1_ram_block[4][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[4][0]
H1_ram_block[4][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[4][0]_PORT_A_address_reg = DFFE(H1_ram_block[4][0]_PORT_A_address, H1_ram_block[4][0]_clock_0, , , H1_ram_block[4][0]_clock_enable_0);
H1_ram_block[4][0]_clock_0 = g_clk;
H1_ram_block[4][0]_clock_enable_0 = VCC;
H1_ram_block[4][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[4][0]_PORT_A_address_reg, , , , , , H1_ram_block[4][0]_clock_0, , H1_ram_block[4][0]_clock_enable_0, , , );
H1_ram_block[4][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[4][0]_PORT_A_data_out, H1_ram_block[4][0]_clock_0, , , H1_ram_block[4][0]_clock_enable_0);
H1_ram_block[4][0] = H1_ram_block[4][0]_PORT_A_data_out_reg[0];


--K1L5 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~263