p_s.tdf

FPGA开发光盘各章节实例的设计工程与源码

parameters
(
	width = 12
);

subdesign p_s
(
	parallel_in[width..1]		: input;
	serial_out					: output;
	clk							: input;
	clr							: input = vcc;
	load_n						: input ;--= gnd;
)

variable
reg[width..1]		:dff;

begin
	reg[].clk = clk;
	reg[].clrn = clr;	
	if (load_n) then
		for j in 1 to width generate
		reg[j].d = parallel_in[j];
		end generate;
	else
		for j in 1 to width-1 generate
		reg[j].d=reg[j+1].q;
		end generate;
		reg[width].d = gnd;
	end if;
		serial_out = reg[1].q;
end;