accumulator.tdf

FPGA开发光盘各章节实例的设计工程与源码

include "lpm_add_sub";

parameters
(
	x_width = 16,
	x_pre   = 15,
	y_width = 12,
	y_pre   = 10,
	out_int = 3,
	out_pre = 15,
	pipeline= "yes"
);

constant dff_num = (x_width-x_pre)+(y_width-y_pre)+out_pre;
constant out_width = out_int + out_pre;

subdesign accumulator
(
	clk						: input;
	clr						: input = vcc;
	datain[x_width..1]		: input;	
	add_sub					: input ;--= vcc;
	f_en					: input ;--= gnd;	
	a_load					: input ;--= gnd;	
	dataout[out_width..1]	: output;	
)

variable
adder						:lpm_add_sub with (lpm_width = x_width+1,
							 lpm_representation = "unsigned");
accum[dff_num..1]			:dff;

if(pipeline == "yes") generate
	flip[out_width..1]		:dffe;
end generate;
	adder_dataa[x_width+1..1]:node;
	adder_datab[x_width+1..1]:node;
	adder_result[x_width+1..1]:node;
	
begin
	accum[].clk = clk;
	accum[].clrn = clr;
	case a_load is
		when vcc =>
			accum[dff_num] = datain[x_width];
			accum[dff_num-1..dff_num-x_width] = datain[];
			if (dff_num-x_width-1>0) generate
			   accum[dff_num-x_width-1..1] = gnd;
			end generate;
		when gnd =>
			accum[dff_num..dff_num-x_width].d = adder_result[];
			accum[dff_num-x_width-1..1].d = accum[dff_num-x_width..2];
	end case;
	
	adder.add_sub = add_sub;
	
	adder_datab[] = (datain[x_width],datain[]);
	adder_dataa[x_width+1] = accum[dff_num];
	adder_dataa[x_width..1]= accum[dff_num..dff_num-x_width+1];
	adder.dataa[] = adder_dataa[];
	adder.datab[] = adder_datab[];
	adder_result[] = adder.result[];	
	
	if(pipeline == "yes") generate
		flip[].clk = clk;
		flip[].clrn = clr;
		flip[].ena = f_en;
		flip[].d = accum[out_width..1].q;
		dataout[] = flip[].q;
	else generate
	 	dataout[] = accum[out_width..1].q;
	end generate;
end;