filter.eqn

FPGA开发光盘各章节实例的设计工程与源码

--K62L6 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~870 and unplaced
--operation mode is normal

K62L6 = H1_ram_block[15][1] & (H1_ram_block[14][1] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[15][1] & H1_ram_block[14][1] & !H1_rdaddress_buffer[1][0];


--H1_ram_block[13][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[13][1] and unplaced
H1_ram_block[13][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[13][1]_PORT_A_address_reg = DFFE(H1_ram_block[13][1]_PORT_A_address, H1_ram_block[13][1]_clock_0, , , H1_ram_block[13][1]_clock_enable_0);
H1_ram_block[13][1]_clock_0 = g_clk;
H1_ram_block[13][1]_clock_enable_0 = VCC;
H1_ram_block[13][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[13][1]_PORT_A_address_reg, , , , , , H1_ram_block[13][1]_clock_0, , H1_ram_block[13][1]_clock_enable_0, , , );
H1_ram_block[13][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[13][1]_PORT_A_data_out, H1_ram_block[13][1]_clock_0, , , H1_ram_block[13][1]_clock_enable_0);
H1_ram_block[13][1] = H1_ram_block[13][1]_PORT_A_data_out_reg[0];


--H1_ram_block[12][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[12][1] and unplaced
H1_ram_block[12][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[12][1]_PORT_A_address_reg = DFFE(H1_ram_block[12][1]_PORT_A_address, H1_ram_block[12][1]_clock_0, , , H1_ram_block[12][1]_clock_enable_0);
H1_ram_block[12][1]_clock_0 = g_clk;
H1_ram_block[12][1]_clock_enable_0 = VCC;
H1_ram_block[12][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[12][1]_PORT_A_address_reg, , , , , , H1_ram_block[12][1]_clock_0, , H1_ram_block[12][1]_clock_enable_0, , , );
H1_ram_block[12][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[12][1]_PORT_A_data_out, H1_ram_block[12][1]_clock_0, , , H1_ram_block[12][1]_clock_enable_0);
H1_ram_block[12][1] = H1_ram_block[12][1]_PORT_A_data_out_reg[0];


--K52L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00018|result_node~7 and unplaced
--operation mode is normal

K52L1 = H1_ram_block[13][1] & (H1_ram_block[12][1] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[13][1] & H1_ram_block[12][1] & !H1_rdaddress_buffer[1][0];


--K62L7 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~876 and unplaced
--operation mode is normal

K62L7 = H1_rdaddress_buffer[1][2] & (H1_rdaddress_buffer[1][1] & K62L6 # !H1_rdaddress_buffer[1][1] & K52L1);


--K62L2 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~35 and unplaced
--operation mode is normal

K62L2 = K62L8 & (K62L5 # K62L7 # !H1_rdaddress_buffer[1][3]);


--H1_ram_block[5][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[5][2] and unplaced
H1_ram_block[5][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[5][2]_PORT_A_address_reg = DFFE(H1_ram_block[5][2]_PORT_A_address, H1_ram_block[5][2]_clock_0, , , H1_ram_block[5][2]_clock_enable_0);
H1_ram_block[5][2]_clock_0 = g_clk;
H1_ram_block[5][2]_clock_enable_0 = VCC;
H1_ram_block[5][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[5][2]_PORT_A_address_reg, , , , , , H1_ram_block[5][2]_clock_0, , H1_ram_block[5][2]_clock_enable_0, , , );
H1_ram_block[5][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[5][2]_PORT_A_data_out, H1_ram_block[5][2]_clock_0, , , H1_ram_block[5][2]_clock_enable_0);
H1_ram_block[5][2] = H1_ram_block[5][2]_PORT_A_data_out_reg[0];


--H1_ram_block[4][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[4][2] and unplaced
H1_ram_block[4][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[4][2]_PORT_A_address_reg = DFFE(H1_ram_block[4][2]_PORT_A_address, H1_ram_block[4][2]_clock_0, , , H1_ram_block[4][2]_clock_enable_0);
H1_ram_block[4][2]_clock_0 = g_clk;
H1_ram_block[4][2]_clock_enable_0 = VCC;
H1_ram_block[4][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[4][2]_PORT_A_address_reg, , , , , , H1_ram_block[4][2]_clock_0, , H1_ram_block[4][2]_clock_enable_0, , , );
H1_ram_block[4][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[4][2]_PORT_A_data_out, H1_ram_block[4][2]_clock_0, , , H1_ram_block[4][2]_clock_enable_0);
H1_ram_block[4][2] = H1_ram_block[4][2]_PORT_A_data_out_reg[0];


--K82L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00014|muxlut:$00014|result_node~1 and unplaced
--operation mode is normal

K82L1 = H1_rdaddress_buffer[1][1] # H1_rdaddress_buffer[1][0] & H1_ram_block[5][2] # !H1_rdaddress_buffer[1][0] & H1_ram_block[4][2];


--H1_ram_block[7][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[7][2] and unplaced
H1_ram_block[7][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[7][2]_PORT_A_address_reg = DFFE(H1_ram_block[7][2]_PORT_A_address, H1_ram_block[7][2]_clock_0, , , H1_ram_block[7][2]_clock_enable_0);
H1_ram_block[7][2]_clock_0 = g_clk;
H1_ram_block[7][2]_clock_enable_0 = VCC;
H1_ram_block[7][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[7][2]_PORT_A_address_reg, , , , , , H1_ram_block[7][2]_clock_0, , H1_ram_block[7][2]_clock_enable_0, , , );
H1_ram_block[7][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[7][2]_PORT_A_data_out, H1_ram_block[7][2]_clock_0, , , H1_ram_block[7][2]_clock_enable_0);
H1_ram_block[7][2] = H1_ram_block[7][2]_PORT_A_data_out_reg[0];


--H1_ram_block[6][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[6][2] and unplaced
H1_ram_block[6][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[6][2]_PORT_A_address_reg = DFFE(H1_ram_block[6][2]_PORT_A_address, H1_ram_block[6][2]_clock_0, , , H1_ram_block[6][2]_clock_enable_0);
H1_ram_block[6][2]_clock_0 = g_clk;
H1_ram_block[6][2]_clock_enable_0 = VCC;
H1_ram_block[6][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[6][2]_PORT_A_address_reg, , , , , , H1_ram_block[6][2]_clock_0, , H1_ram_block[6][2]_clock_enable_0, , , );
H1_ram_block[6][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[6][2]_PORT_A_data_out, H1_ram_block[6][2]_clock_0, , , H1_ram_block[6][2]_clock_enable_0);
H1_ram_block[6][2] = H1_ram_block[6][2]_PORT_A_data_out_reg[0];


--K13L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00014|muxlut:$00020|result_node~13 and unplaced
--operation mode is normal

K13L1 = H1_rdaddress_buffer[1][0] & H1_ram_block[7][2] # !H1_rdaddress_buffer[1][0] & H1_ram_block[6][2] # !H1_rdaddress_buffer[1][1];


--K13L9 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00014|muxlut:$00020|result_node~933 and unplaced
--operation mode is normal

K13L9 = H1_rdaddress_buffer[1][3] # K82L1 & H1_rdaddress_buffer[1][2] & K13L1;


--H1_ram_block[1][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[1][2] and unplaced
H1_ram_block[1][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[1][2]_PORT_A_address_reg = DFFE(H1_ram_block[1][2]_PORT_A_address, H1_ram_block[1][2]_clock_0, , , H1_ram_block[1][2]_clock_enable_0);
H1_ram_block[1][2]_clock_0 = g_clk;
H1_ram_block[1][2]_clock_enable_0 = VCC;
H1_ram_block[1][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[1][2]_PORT_A_address_reg, , , , , , H1_ram_block[1][2]_clock_0, , H1_ram_block[1][2]_clock_enable_0, , , );
H1_ram_block[1][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[1][2]_PORT_A_data_out, H1_ram_block[1][2]_clock_0, , , H1_ram_block[1][2]_clock_enable_0);
H1_ram_block[1][2] = H1_ram_block[1][2]_PORT_A_data_out_reg[0];


--H1_ram_block[0][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][2] and unplaced
H1_ram_block[0][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][2]_PORT_A_address_reg = DFFE(H1_ram_block[0][2]_PORT_A_address, H1_ram_block[0][2]_clock_0, , , H1_ram_block[0][2]_clock_enable_0);
H1_ram_block[0][2]_clock_0 = g_clk;
H1_ram_block[0][2]_clock_enable_0 = VCC;
H1_ram_block[0][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][2]_PORT_A_address_reg, , , , , , H1_ram_block[0][2]_clock_0, , H1_ram_block[0][2]_clock_enable_0, , , );
H1_ram_block[0][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][2]_PORT_A_data_out, H1_ram_block[0][2]_clock_0, , , H1_ram_block[0][2]_clock_enable_0);
H1_ram_block[0][2] = H1_ram_block[0][2]_PORT_A_data_out_reg[0];


--K72L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00014|muxlut:$00012|result_node~1 and unplaced
--operation mode is normal

K72L1 = H1_rdaddress_buffer[1][1] # H1_rdaddress_buffer[1][0] & H1_ram_block[1][2] # !H1_rdaddress_buffer[1][0] & H1_ram_block[0][2];


--H1_ram_block[3][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][2] and unplaced
H1_ram_block[3][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][2]_PORT_A_address_reg = DFFE(H1_ram_block[3][2]_PORT_A_address, H1_ram_block[3][2]_clock_0, , , H1_ram_block[3][2]_clock_enable_0);
H1_ram_block[3][2]_clock_0 = g_clk;
H1_ram_block[3][2]_clock_enable_0 = VCC;
H1_ram_block[3][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][2]_PORT_A_address_reg, , , , , , H1_ram_block[3][2]_clock_0, , H1_ram_block[3][2]_clock_enable_0, , , );
H1_ram_block[3][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][2]_PORT_A_data_out, H1_ram_block[3][2]_clock_0, , , H1_ram_block[3][2]_clock_enable_0);
H1_ram_block[3][2] = H1_ram_block[3][2]_PORT_A_data_out_reg[0];


--H1_ram_block[2][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[2][2] and unplaced
H1_ram_block[2][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[2][2]_PORT_A_address_reg = DFFE(H1_ram_block[2][2]_PORT_A_address, H1_ram_block[2][2]_clock_0, , , H1_ram_block[2][2]_clock_enable_0);
H1_ram_block[2][2]_clock_0 = g_clk;
H1_ram_block[2][2]_clock_enable_0 = VCC;
H1_ram_block[2][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[2][2]_PORT_A_address_reg, , , , , , H1_ram_block[2][2]_clock_0, , H1_ram_block[2][2]_clock_enable_0, , , );
H1_ram_block[2][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[2][2]_PORT_A_data_out, H1_ram_block[2][2]_clock_0, , , H1_ram_block[2][2]_clock_enable_0);
H1_ram_block[2][2] = H1_ram_block[2][2]_PORT_A_data_out_reg[0];


--K13L3 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00014|muxlut:$00020|result_node~36 and unplaced
--operation mode is normal

K13L3 = H1_rdaddress_buffer[1][0] & H1_ram_block[3][2] # !H1_rdaddress_buffer[1][0] & H1_ram_block[2][2] # !H1_rdaddress_buffer[1][1];


--K13L8 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00014|muxlut:$00020|result_node~928 and unplaced
--operation mode is normal

K13L8 = K13L9 # K72L1 & K13L3 & !H1_rdaddress_buffer[1][2];


--H1_ram_block[11][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][2] and unplaced
H1_ram_block[11][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][2]_PORT_A_address_reg = DFFE(H1_ram_block[11][2]_PORT_A_address, H1_ram_block[11][2]_clock_0, , , H1_ram_block[11][2]_clock_enable_0);
H1_ram_block[11][2]_clock_0 = g_clk;
H1_ram_block[11][2]_clock_enable_0 = VCC;
H1_ram_block[11][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][2]_PORT_A_address_reg, , , , , , H1_ram_block[11][2]_clock_0, , H1_ram_block[11][2]_clock_enable_0, , , );
H1_ram_block[11][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][2]_PORT_A_data_out, H1_ram_block[11][2]_clock_0, , , H1_ram_block[11][2]_clock_enable_0);
H1_ram_block[11][2] = H1_ram_block[11][2]_PORT_A_data_out_reg[0];


--H1_ram_block[10][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[10][2] and unplaced
H1_ram_block[10][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[10][2]_PORT_A_address_reg = DFFE(H1_ram_block[10][2]_PORT_A_address, H1_ram_block[10][2]_clock_0, , , H1_ram_block[10][2]_clock_enable_0);
H1_ram_block[10][2]_clock_0 = g_clk;
H1_ram_block[10][2]_clock_enable_0 = VCC;
H1_ram_block[10][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[10][2]_PORT_A_address_reg, , , , , , H1_ram_block[10][2]_clock_0, , H1_ram_block[10][2]_clock_enable_0, , , );
H1_ram_block[10][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[10][2]_PORT_A_data_out, H1_ram_block[10][2]_clock_0, , , H1_ram_block[10][2]_clock_enable_0);
H1_ram_block[10][2] = H1_ram_block[10][2]_PORT_A_data_out_reg[0];


--K13L4 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00014|muxlut:$00020|result_node~856 and unplaced
--operation mode is normal

K13L4 = H1_ram_block[11][2] & (H1_ram_block[10][2] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[11][2] & H1_ram_block[10][2] & !H1_rdaddress_buffer[1][0];


--H1_ram_block[9][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[9][2] and unplaced
H1_ram_block[9][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[9][2]_PORT_A_address_reg = DFFE(H1_ram_block[9][2]_PORT_A_address, H1_ram_block[9][2]_clock_0, , , H1_ram_block[9][2]_clock_enable_0);
H1_ram_block[9][2]_clock_0 = g_clk;
H1_ram_block[9][2]_clock_enable_0 = VCC;
H1_ram_block[9][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[9][2]_PORT_A_address_reg, , , , , , H1_ram_block[9][2]_clock_0, , H1_ram_block[9][2]_clock_enable_0, , , );
H1_ram_block[9][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[9][2]_PORT_A_data_out, H1_ram_block[9][2]_clock_0, , , H1_ram_block[9][2]_clock_enable_0);
H1_ram_block[9][2] = H1_ram_block[9][2]_PORT_A_data_out_reg[0];


--H1_ram_block[8][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][2] and unplaced
H1_ram_block[8][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][2]_PORT_A_address_reg = DFFE(H1_ram_block[8][2]_PORT_A_address, H1_ram_block[8][2]_clock_0, , , H1_ram_block[8][2]_clock_enable_0);
H1_ram_block[8][2]_clock_0 = g_clk;
H1_ram_block[8][2]_clock_enable_0 = VCC;
H1_ram_block[8][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][2]_PORT_A_address_reg, , , , , , H1_ram_block[8][2]_clock_0, , H1_ram_block[8][2]_clock_enable_0, , , );
H1_ram_block[8][2]_PO