filter.eqn

FPGA开发光盘各章节实例的设计工程与源码

K02L1 = H1_ram_block[13][0] & (H1_ram_block[12][0] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[13][0] & H1_ram_block[12][0] & !H1_rdaddress_buffer[1][0];


--K12L7 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~876 and unplaced
--operation mode is normal

K12L7 = H1_rdaddress_buffer[1][2] & (H1_rdaddress_buffer[1][1] & K12L6 # !H1_rdaddress_buffer[1][1] & K02L1);


--K12L2 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~35 and unplaced
--operation mode is normal

K12L2 = K12L8 & (K12L5 # K12L7 # !H1_rdaddress_buffer[1][3]);


--H1_ram_block[5][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[5][1] and unplaced
H1_ram_block[5][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[5][1]_PORT_A_address_reg = DFFE(H1_ram_block[5][1]_PORT_A_address, H1_ram_block[5][1]_clock_0, , , H1_ram_block[5][1]_clock_enable_0);
H1_ram_block[5][1]_clock_0 = g_clk;
H1_ram_block[5][1]_clock_enable_0 = VCC;
H1_ram_block[5][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[5][1]_PORT_A_address_reg, , , , , , H1_ram_block[5][1]_clock_0, , H1_ram_block[5][1]_clock_enable_0, , , );
H1_ram_block[5][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[5][1]_PORT_A_data_out, H1_ram_block[5][1]_clock_0, , , H1_ram_block[5][1]_clock_enable_0);
H1_ram_block[5][1] = H1_ram_block[5][1]_PORT_A_data_out_reg[0];


--H1_ram_block[4][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[4][1] and unplaced
H1_ram_block[4][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[4][1]_PORT_A_address_reg = DFFE(H1_ram_block[4][1]_PORT_A_address, H1_ram_block[4][1]_clock_0, , , H1_ram_block[4][1]_clock_enable_0);
H1_ram_block[4][1]_clock_0 = g_clk;
H1_ram_block[4][1]_clock_enable_0 = VCC;
H1_ram_block[4][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[4][1]_PORT_A_address_reg, , , , , , H1_ram_block[4][1]_clock_0, , H1_ram_block[4][1]_clock_enable_0, , , );
H1_ram_block[4][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[4][1]_PORT_A_data_out, H1_ram_block[4][1]_clock_0, , , H1_ram_block[4][1]_clock_enable_0);
H1_ram_block[4][1] = H1_ram_block[4][1]_PORT_A_data_out_reg[0];


--K32L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00014|result_node~1 and unplaced
--operation mode is normal

K32L1 = H1_rdaddress_buffer[1][1] # H1_rdaddress_buffer[1][0] & H1_ram_block[5][1] # !H1_rdaddress_buffer[1][0] & H1_ram_block[4][1];


--H1_ram_block[7][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[7][1] and unplaced
H1_ram_block[7][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[7][1]_PORT_A_address_reg = DFFE(H1_ram_block[7][1]_PORT_A_address, H1_ram_block[7][1]_clock_0, , , H1_ram_block[7][1]_clock_enable_0);
H1_ram_block[7][1]_clock_0 = g_clk;
H1_ram_block[7][1]_clock_enable_0 = VCC;
H1_ram_block[7][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[7][1]_PORT_A_address_reg, , , , , , H1_ram_block[7][1]_clock_0, , H1_ram_block[7][1]_clock_enable_0, , , );
H1_ram_block[7][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[7][1]_PORT_A_data_out, H1_ram_block[7][1]_clock_0, , , H1_ram_block[7][1]_clock_enable_0);
H1_ram_block[7][1] = H1_ram_block[7][1]_PORT_A_data_out_reg[0];


--H1_ram_block[6][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[6][1] and unplaced
H1_ram_block[6][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[6][1]_PORT_A_address_reg = DFFE(H1_ram_block[6][1]_PORT_A_address, H1_ram_block[6][1]_clock_0, , , H1_ram_block[6][1]_clock_enable_0);
H1_ram_block[6][1]_clock_0 = g_clk;
H1_ram_block[6][1]_clock_enable_0 = VCC;
H1_ram_block[6][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[6][1]_PORT_A_address_reg, , , , , , H1_ram_block[6][1]_clock_0, , H1_ram_block[6][1]_clock_enable_0, , , );
H1_ram_block[6][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[6][1]_PORT_A_data_out, H1_ram_block[6][1]_clock_0, , , H1_ram_block[6][1]_clock_enable_0);
H1_ram_block[6][1] = H1_ram_block[6][1]_PORT_A_data_out_reg[0];


--K62L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~13 and unplaced
--operation mode is normal

K62L1 = H1_rdaddress_buffer[1][0] & H1_ram_block[7][1] # !H1_rdaddress_buffer[1][0] & H1_ram_block[6][1] # !H1_rdaddress_buffer[1][1];


--K62L9 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~933 and unplaced
--operation mode is normal

K62L9 = H1_rdaddress_buffer[1][3] # K32L1 & H1_rdaddress_buffer[1][2] & K62L1;


--H1_ram_block[1][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[1][1] and unplaced
H1_ram_block[1][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[1][1]_PORT_A_address_reg = DFFE(H1_ram_block[1][1]_PORT_A_address, H1_ram_block[1][1]_clock_0, , , H1_ram_block[1][1]_clock_enable_0);
H1_ram_block[1][1]_clock_0 = g_clk;
H1_ram_block[1][1]_clock_enable_0 = VCC;
H1_ram_block[1][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[1][1]_PORT_A_address_reg, , , , , , H1_ram_block[1][1]_clock_0, , H1_ram_block[1][1]_clock_enable_0, , , );
H1_ram_block[1][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[1][1]_PORT_A_data_out, H1_ram_block[1][1]_clock_0, , , H1_ram_block[1][1]_clock_enable_0);
H1_ram_block[1][1] = H1_ram_block[1][1]_PORT_A_data_out_reg[0];


--H1_ram_block[0][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][1] and unplaced
H1_ram_block[0][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][1]_PORT_A_address_reg = DFFE(H1_ram_block[0][1]_PORT_A_address, H1_ram_block[0][1]_clock_0, , , H1_ram_block[0][1]_clock_enable_0);
H1_ram_block[0][1]_clock_0 = g_clk;
H1_ram_block[0][1]_clock_enable_0 = VCC;
H1_ram_block[0][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][1]_PORT_A_address_reg, , , , , , H1_ram_block[0][1]_clock_0, , H1_ram_block[0][1]_clock_enable_0, , , );
H1_ram_block[0][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][1]_PORT_A_data_out, H1_ram_block[0][1]_clock_0, , , H1_ram_block[0][1]_clock_enable_0);
H1_ram_block[0][1] = H1_ram_block[0][1]_PORT_A_data_out_reg[0];


--K22L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00012|result_node~1 and unplaced
--operation mode is normal

K22L1 = H1_rdaddress_buffer[1][1] # H1_rdaddress_buffer[1][0] & H1_ram_block[1][1] # !H1_rdaddress_buffer[1][0] & H1_ram_block[0][1];


--H1_ram_block[3][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][1] and unplaced
H1_ram_block[3][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][1]_PORT_A_address_reg = DFFE(H1_ram_block[3][1]_PORT_A_address, H1_ram_block[3][1]_clock_0, , , H1_ram_block[3][1]_clock_enable_0);
H1_ram_block[3][1]_clock_0 = g_clk;
H1_ram_block[3][1]_clock_enable_0 = VCC;
H1_ram_block[3][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][1]_PORT_A_address_reg, , , , , , H1_ram_block[3][1]_clock_0, , H1_ram_block[3][1]_clock_enable_0, , , );
H1_ram_block[3][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][1]_PORT_A_data_out, H1_ram_block[3][1]_clock_0, , , H1_ram_block[3][1]_clock_enable_0);
H1_ram_block[3][1] = H1_ram_block[3][1]_PORT_A_data_out_reg[0];


--H1_ram_block[2][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[2][1] and unplaced
H1_ram_block[2][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[2][1]_PORT_A_address_reg = DFFE(H1_ram_block[2][1]_PORT_A_address, H1_ram_block[2][1]_clock_0, , , H1_ram_block[2][1]_clock_enable_0);
H1_ram_block[2][1]_clock_0 = g_clk;
H1_ram_block[2][1]_clock_enable_0 = VCC;
H1_ram_block[2][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[2][1]_PORT_A_address_reg, , , , , , H1_ram_block[2][1]_clock_0, , H1_ram_block[2][1]_clock_enable_0, , , );
H1_ram_block[2][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[2][1]_PORT_A_data_out, H1_ram_block[2][1]_clock_0, , , H1_ram_block[2][1]_clock_enable_0);
H1_ram_block[2][1] = H1_ram_block[2][1]_PORT_A_data_out_reg[0];


--K62L3 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~36 and unplaced
--operation mode is normal

K62L3 = H1_rdaddress_buffer[1][0] & H1_ram_block[3][1] # !H1_rdaddress_buffer[1][0] & H1_ram_block[2][1] # !H1_rdaddress_buffer[1][1];


--K62L8 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~928 and unplaced
--operation mode is normal

K62L8 = K62L9 # K22L1 & K62L3 & !H1_rdaddress_buffer[1][2];


--H1_ram_block[11][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][1] and unplaced
H1_ram_block[11][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][1]_PORT_A_address_reg = DFFE(H1_ram_block[11][1]_PORT_A_address, H1_ram_block[11][1]_clock_0, , , H1_ram_block[11][1]_clock_enable_0);
H1_ram_block[11][1]_clock_0 = g_clk;
H1_ram_block[11][1]_clock_enable_0 = VCC;
H1_ram_block[11][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][1]_PORT_A_address_reg, , , , , , H1_ram_block[11][1]_clock_0, , H1_ram_block[11][1]_clock_enable_0, , , );
H1_ram_block[11][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][1]_PORT_A_data_out, H1_ram_block[11][1]_clock_0, , , H1_ram_block[11][1]_clock_enable_0);
H1_ram_block[11][1] = H1_ram_block[11][1]_PORT_A_data_out_reg[0];


--H1_ram_block[10][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[10][1] and unplaced
H1_ram_block[10][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[10][1]_PORT_A_address_reg = DFFE(H1_ram_block[10][1]_PORT_A_address, H1_ram_block[10][1]_clock_0, , , H1_ram_block[10][1]_clock_enable_0);
H1_ram_block[10][1]_clock_0 = g_clk;
H1_ram_block[10][1]_clock_enable_0 = VCC;
H1_ram_block[10][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[10][1]_PORT_A_address_reg, , , , , , H1_ram_block[10][1]_clock_0, , H1_ram_block[10][1]_clock_enable_0, , , );
H1_ram_block[10][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[10][1]_PORT_A_data_out, H1_ram_block[10][1]_clock_0, , , H1_ram_block[10][1]_clock_enable_0);
H1_ram_block[10][1] = H1_ram_block[10][1]_PORT_A_data_out_reg[0];


--K62L4 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~856 and unplaced
--operation mode is normal

K62L4 = H1_ram_block[11][1] & (H1_ram_block[10][1] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[11][1] & H1_ram_block[10][1] & !H1_rdaddress_buffer[1][0];


--H1_ram_block[9][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[9][1] and unplaced
H1_ram_block[9][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[9][1]_PORT_A_address_reg = DFFE(H1_ram_block[9][1]_PORT_A_address, H1_ram_block[9][1]_clock_0, , , H1_ram_block[9][1]_clock_enable_0);
H1_ram_block[9][1]_clock_0 = g_clk;
H1_ram_block[9][1]_clock_enable_0 = VCC;
H1_ram_block[9][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[9][1]_PORT_A_address_reg, , , , , , H1_ram_block[9][1]_clock_0, , H1_ram_block[9][1]_clock_enable_0, , , );
H1_ram_block[9][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[9][1]_PORT_A_data_out, H1_ram_block[9][1]_clock_0, , , H1_ram_block[9][1]_clock_enable_0);
H1_ram_block[9][1] = H1_ram_block[9][1]_PORT_A_data_out_reg[0];


--H1_ram_block[8][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][1] and unplaced
H1_ram_block[8][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][1]_PORT_A_address_reg = DFFE(H1_ram_block[8][1]_PORT_A_address, H1_ram_block[8][1]_clock_0, , , H1_ram_block[8][1]_clock_enable_0);
H1_ram_block[8][1]_clock_0 = g_clk;
H1_ram_block[8][1]_clock_enable_0 = VCC;
H1_ram_block[8][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][1]_PORT_A_address_reg, , , , , , H1_ram_block[8][1]_clock_0, , H1_ram_block[8][1]_clock_enable_0, , , );
H1_ram_block[8][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[8][1]_PORT_A_data_out, H1_ram_block[8][1]_clock_0, , , H1_ram_block[8][1]_clock_enable_0);
H1_ram_block[8][1] = H1_ram_block[8][1]_PORT_A_data_out_reg[0];


--K42L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00016|result_node~7 and unplaced
--operation mode is normal

K42L1 = H1_ram_block[9][1] & (H1_ram_block[8][1] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[9][1] & H1_ram_block[8][1] & !H1_rdaddress_buffer[1][0];


--K62L5 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00012|muxlut:$00020|result_node~862 and unplaced
--operation mode is normal

K62L5 = !H1_rdaddress_buffer[1][2] & (H1_rdaddress_buffer[1][1] & K62L4 # !H1_rdaddress_buffer[1][1] & K42L1);


--H1_ram_block[15][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[15][1] and unplaced
H1_ram_block[15][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[15][1]_PORT_A_address_reg = DFFE(H1_ram_block[15][1]_PORT_A_address, H1_ram_block[15][1]_clock_0, , , H1_ram_block[15][1]_clock_enable_0);
H1_ram_block[15][1]_clock_0 = g_clk;
H1_ram_block[15][1]_clock_enable_0 = VCC;
H1_ram_block[15][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[15][1]_PORT_A_address_reg, , , , , , H1_ram_block[15][1]_clock_0, , H1_ram_block[15][1]_clock_enable_0, , , );
H1_ram_block[15][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[15][1]_PORT_A_data_out, H1_ram_block[15][1]_clock_0, , , H1_ram_block[15][1]_clock_enable_0);
H1_ram_block[15][1] = H1_ram_block[15][1]_PORT_A_data_out_reg[0];


--H1_ram_block[14][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[14][1] and unplaced
H1_ram_block[14][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[14][1]_PORT_A_address_reg = DFFE(H1_ram_block[14][1]_PORT_A_address, H1_ram_block[14][1]_clock_0, , , H1_ram_block[14][1]_clock_enable_0);
H1_ram_block[14][1]_clock_0 = g_clk;
H1_ram_block[14][1]_clock_enable_0 = VCC;
H1_ram_block[14][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[14][1]_PORT_A_address_reg, , , , , , H1_ram_block[14][1]_clock_0, , H1_ram_block[14][1]_clock_enable_0, , , );
H1_ram_block[14][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[14][1]_PORT_A_data_out, H1_ram_block[14][1]_clock_0, , , H1_ram_block[14][1]_clock_enable_0);
H1_ram_block[14][1] = H1_ram_block[14][1]_PORT_A_data_out_reg[0];