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📄 filter.eqn

📁 FPGA开发光盘各章节实例的设计工程与源码
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--operation mode is normal

K81L1 = H1_rdaddress_buffer[1][1] # H1_rdaddress_buffer[1][0] & H1_ram_block[5][0] # !H1_rdaddress_buffer[1][0] & H1_ram_block[4][0];


--H1_rdaddress_buffer[1][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][2] and unplaced
--operation mode is normal

H1_rdaddress_buffer[1][2]_lut_out = H1_rdaddress_buffer[0][2];
H1_rdaddress_buffer[1][2] = DFFEA(H1_rdaddress_buffer[1][2]_lut_out, g_clk, VCC, , , );


--H1_ram_block[7][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[7][0] and unplaced
H1_ram_block[7][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[7][0]_PORT_A_address_reg = DFFE(H1_ram_block[7][0]_PORT_A_address, H1_ram_block[7][0]_clock_0, , , H1_ram_block[7][0]_clock_enable_0);
H1_ram_block[7][0]_clock_0 = g_clk;
H1_ram_block[7][0]_clock_enable_0 = VCC;
H1_ram_block[7][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[7][0]_PORT_A_address_reg, , , , , , H1_ram_block[7][0]_clock_0, , H1_ram_block[7][0]_clock_enable_0, , , );
H1_ram_block[7][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[7][0]_PORT_A_data_out, H1_ram_block[7][0]_clock_0, , , H1_ram_block[7][0]_clock_enable_0);
H1_ram_block[7][0] = H1_ram_block[7][0]_PORT_A_data_out_reg[0];


--H1_ram_block[6][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[6][0] and unplaced
H1_ram_block[6][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[6][0]_PORT_A_address_reg = DFFE(H1_ram_block[6][0]_PORT_A_address, H1_ram_block[6][0]_clock_0, , , H1_ram_block[6][0]_clock_enable_0);
H1_ram_block[6][0]_clock_0 = g_clk;
H1_ram_block[6][0]_clock_enable_0 = VCC;
H1_ram_block[6][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[6][0]_PORT_A_address_reg, , , , , , H1_ram_block[6][0]_clock_0, , H1_ram_block[6][0]_clock_enable_0, , , );
H1_ram_block[6][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[6][0]_PORT_A_data_out, H1_ram_block[6][0]_clock_0, , , H1_ram_block[6][0]_clock_enable_0);
H1_ram_block[6][0] = H1_ram_block[6][0]_PORT_A_data_out_reg[0];


--K12L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~13 and unplaced
--operation mode is normal

K12L1 = H1_rdaddress_buffer[1][0] & H1_ram_block[7][0] # !H1_rdaddress_buffer[1][0] & H1_ram_block[6][0] # !H1_rdaddress_buffer[1][1];


--K12L9 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~933 and unplaced
--operation mode is normal

K12L9 = H1_rdaddress_buffer[1][3] # K81L1 & H1_rdaddress_buffer[1][2] & K12L1;


--H1_ram_block[1][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[1][0] and unplaced
H1_ram_block[1][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[1][0]_PORT_A_address_reg = DFFE(H1_ram_block[1][0]_PORT_A_address, H1_ram_block[1][0]_clock_0, , , H1_ram_block[1][0]_clock_enable_0);
H1_ram_block[1][0]_clock_0 = g_clk;
H1_ram_block[1][0]_clock_enable_0 = VCC;
H1_ram_block[1][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[1][0]_PORT_A_address_reg, , , , , , H1_ram_block[1][0]_clock_0, , H1_ram_block[1][0]_clock_enable_0, , , );
H1_ram_block[1][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[1][0]_PORT_A_data_out, H1_ram_block[1][0]_clock_0, , , H1_ram_block[1][0]_clock_enable_0);
H1_ram_block[1][0] = H1_ram_block[1][0]_PORT_A_data_out_reg[0];


--H1_ram_block[0][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][0] and unplaced
H1_ram_block[0][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][0]_PORT_A_address_reg = DFFE(H1_ram_block[0][0]_PORT_A_address, H1_ram_block[0][0]_clock_0, , , H1_ram_block[0][0]_clock_enable_0);
H1_ram_block[0][0]_clock_0 = g_clk;
H1_ram_block[0][0]_clock_enable_0 = VCC;
H1_ram_block[0][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][0]_PORT_A_address_reg, , , , , , H1_ram_block[0][0]_clock_0, , H1_ram_block[0][0]_clock_enable_0, , , );
H1_ram_block[0][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][0]_PORT_A_data_out, H1_ram_block[0][0]_clock_0, , , H1_ram_block[0][0]_clock_enable_0);
H1_ram_block[0][0] = H1_ram_block[0][0]_PORT_A_data_out_reg[0];


--K71L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00012|result_node~1 and unplaced
--operation mode is normal

K71L1 = H1_rdaddress_buffer[1][1] # H1_rdaddress_buffer[1][0] & H1_ram_block[1][0] # !H1_rdaddress_buffer[1][0] & H1_ram_block[0][0];


--H1_ram_block[3][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][0] and unplaced
H1_ram_block[3][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][0]_PORT_A_address_reg = DFFE(H1_ram_block[3][0]_PORT_A_address, H1_ram_block[3][0]_clock_0, , , H1_ram_block[3][0]_clock_enable_0);
H1_ram_block[3][0]_clock_0 = g_clk;
H1_ram_block[3][0]_clock_enable_0 = VCC;
H1_ram_block[3][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][0]_PORT_A_address_reg, , , , , , H1_ram_block[3][0]_clock_0, , H1_ram_block[3][0]_clock_enable_0, , , );
H1_ram_block[3][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][0]_PORT_A_data_out, H1_ram_block[3][0]_clock_0, , , H1_ram_block[3][0]_clock_enable_0);
H1_ram_block[3][0] = H1_ram_block[3][0]_PORT_A_data_out_reg[0];


--H1_ram_block[2][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[2][0] and unplaced
H1_ram_block[2][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[2][0]_PORT_A_address_reg = DFFE(H1_ram_block[2][0]_PORT_A_address, H1_ram_block[2][0]_clock_0, , , H1_ram_block[2][0]_clock_enable_0);
H1_ram_block[2][0]_clock_0 = g_clk;
H1_ram_block[2][0]_clock_enable_0 = VCC;
H1_ram_block[2][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[2][0]_PORT_A_address_reg, , , , , , H1_ram_block[2][0]_clock_0, , H1_ram_block[2][0]_clock_enable_0, , , );
H1_ram_block[2][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[2][0]_PORT_A_data_out, H1_ram_block[2][0]_clock_0, , , H1_ram_block[2][0]_clock_enable_0);
H1_ram_block[2][0] = H1_ram_block[2][0]_PORT_A_data_out_reg[0];


--K12L3 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~36 and unplaced
--operation mode is normal

K12L3 = H1_rdaddress_buffer[1][0] & H1_ram_block[3][0] # !H1_rdaddress_buffer[1][0] & H1_ram_block[2][0] # !H1_rdaddress_buffer[1][1];


--K12L8 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~928 and unplaced
--operation mode is normal

K12L8 = K12L9 # K71L1 & K12L3 & !H1_rdaddress_buffer[1][2];


--H1_ram_block[11][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][0] and unplaced
H1_ram_block[11][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][0]_PORT_A_address_reg = DFFE(H1_ram_block[11][0]_PORT_A_address, H1_ram_block[11][0]_clock_0, , , H1_ram_block[11][0]_clock_enable_0);
H1_ram_block[11][0]_clock_0 = g_clk;
H1_ram_block[11][0]_clock_enable_0 = VCC;
H1_ram_block[11][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][0]_PORT_A_address_reg, , , , , , H1_ram_block[11][0]_clock_0, , H1_ram_block[11][0]_clock_enable_0, , , );
H1_ram_block[11][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][0]_PORT_A_data_out, H1_ram_block[11][0]_clock_0, , , H1_ram_block[11][0]_clock_enable_0);
H1_ram_block[11][0] = H1_ram_block[11][0]_PORT_A_data_out_reg[0];


--H1_ram_block[10][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[10][0] and unplaced
H1_ram_block[10][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[10][0]_PORT_A_address_reg = DFFE(H1_ram_block[10][0]_PORT_A_address, H1_ram_block[10][0]_clock_0, , , H1_ram_block[10][0]_clock_enable_0);
H1_ram_block[10][0]_clock_0 = g_clk;
H1_ram_block[10][0]_clock_enable_0 = VCC;
H1_ram_block[10][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[10][0]_PORT_A_address_reg, , , , , , H1_ram_block[10][0]_clock_0, , H1_ram_block[10][0]_clock_enable_0, , , );
H1_ram_block[10][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[10][0]_PORT_A_data_out, H1_ram_block[10][0]_clock_0, , , H1_ram_block[10][0]_clock_enable_0);
H1_ram_block[10][0] = H1_ram_block[10][0]_PORT_A_data_out_reg[0];


--K12L4 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~856 and unplaced
--operation mode is normal

K12L4 = H1_ram_block[11][0] & (H1_ram_block[10][0] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[11][0] & H1_ram_block[10][0] & !H1_rdaddress_buffer[1][0];


--H1_ram_block[9][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[9][0] and unplaced
H1_ram_block[9][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[9][0]_PORT_A_address_reg = DFFE(H1_ram_block[9][0]_PORT_A_address, H1_ram_block[9][0]_clock_0, , , H1_ram_block[9][0]_clock_enable_0);
H1_ram_block[9][0]_clock_0 = g_clk;
H1_ram_block[9][0]_clock_enable_0 = VCC;
H1_ram_block[9][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[9][0]_PORT_A_address_reg, , , , , , H1_ram_block[9][0]_clock_0, , H1_ram_block[9][0]_clock_enable_0, , , );
H1_ram_block[9][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[9][0]_PORT_A_data_out, H1_ram_block[9][0]_clock_0, , , H1_ram_block[9][0]_clock_enable_0);
H1_ram_block[9][0] = H1_ram_block[9][0]_PORT_A_data_out_reg[0];


--H1_ram_block[8][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][0] and unplaced
H1_ram_block[8][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][0]_PORT_A_address_reg = DFFE(H1_ram_block[8][0]_PORT_A_address, H1_ram_block[8][0]_clock_0, , , H1_ram_block[8][0]_clock_enable_0);
H1_ram_block[8][0]_clock_0 = g_clk;
H1_ram_block[8][0]_clock_enable_0 = VCC;
H1_ram_block[8][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][0]_PORT_A_address_reg, , , , , , H1_ram_block[8][0]_clock_0, , H1_ram_block[8][0]_clock_enable_0, , , );
H1_ram_block[8][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[8][0]_PORT_A_data_out, H1_ram_block[8][0]_clock_0, , , H1_ram_block[8][0]_clock_enable_0);
H1_ram_block[8][0] = H1_ram_block[8][0]_PORT_A_data_out_reg[0];


--K91L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00016|result_node~7 and unplaced
--operation mode is normal

K91L1 = H1_ram_block[9][0] & (H1_ram_block[8][0] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[9][0] & H1_ram_block[8][0] & !H1_rdaddress_buffer[1][0];


--K12L5 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~862 and unplaced
--operation mode is normal

K12L5 = !H1_rdaddress_buffer[1][2] & (H1_rdaddress_buffer[1][1] & K12L4 # !H1_rdaddress_buffer[1][1] & K91L1);


--H1_ram_block[15][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[15][0] and unplaced
H1_ram_block[15][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[15][0]_PORT_A_address_reg = DFFE(H1_ram_block[15][0]_PORT_A_address, H1_ram_block[15][0]_clock_0, , , H1_ram_block[15][0]_clock_enable_0);
H1_ram_block[15][0]_clock_0 = g_clk;
H1_ram_block[15][0]_clock_enable_0 = VCC;
H1_ram_block[15][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[15][0]_PORT_A_address_reg, , , , , , H1_ram_block[15][0]_clock_0, , H1_ram_block[15][0]_clock_enable_0, , , );
H1_ram_block[15][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[15][0]_PORT_A_data_out, H1_ram_block[15][0]_clock_0, , , H1_ram_block[15][0]_clock_enable_0);
H1_ram_block[15][0] = H1_ram_block[15][0]_PORT_A_data_out_reg[0];


--H1_ram_block[14][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[14][0] and unplaced
H1_ram_block[14][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[14][0]_PORT_A_address_reg = DFFE(H1_ram_block[14][0]_PORT_A_address, H1_ram_block[14][0]_clock_0, , , H1_ram_block[14][0]_clock_enable_0);
H1_ram_block[14][0]_clock_0 = g_clk;
H1_ram_block[14][0]_clock_enable_0 = VCC;
H1_ram_block[14][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[14][0]_PORT_A_address_reg, , , , , , H1_ram_block[14][0]_clock_0, , H1_ram_block[14][0]_clock_enable_0, , , );
H1_ram_block[14][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[14][0]_PORT_A_data_out, H1_ram_block[14][0]_clock_0, , , H1_ram_block[14][0]_clock_enable_0);
H1_ram_block[14][0] = H1_ram_block[14][0]_PORT_A_data_out_reg[0];


--K12L6 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~870 and unplaced
--operation mode is normal

K12L6 = H1_ram_block[15][0] & (H1_ram_block[14][0] # H1_rdaddress_buffer[1][0]) # !H1_ram_block[15][0] & H1_ram_block[14][0] & !H1_rdaddress_buffer[1][0];


--H1_ram_block[13][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[13][0] and unplaced
H1_ram_block[13][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[13][0]_PORT_A_address_reg = DFFE(H1_ram_block[13][0]_PORT_A_address, H1_ram_block[13][0]_clock_0, , , H1_ram_block[13][0]_clock_enable_0);
H1_ram_block[13][0]_clock_0 = g_clk;
H1_ram_block[13][0]_clock_enable_0 = VCC;
H1_ram_block[13][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[13][0]_PORT_A_address_reg, , , , , , H1_ram_block[13][0]_clock_0, , H1_ram_block[13][0]_clock_enable_0, , , );
H1_ram_block[13][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[13][0]_PORT_A_data_out, H1_ram_block[13][0]_clock_0, , , H1_ram_block[13][0]_clock_enable_0);
H1_ram_block[13][0] = H1_ram_block[13][0]_PORT_A_data_out_reg[0];


--H1_ram_block[12][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[12][0] and unplaced
H1_ram_block[12][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[12][0]_PORT_A_address_reg = DFFE(H1_ram_block[12][0]_PORT_A_address, H1_ram_block[12][0]_clock_0, , , H1_ram_block[12][0]_clock_enable_0);
H1_ram_block[12][0]_clock_0 = g_clk;
H1_ram_block[12][0]_clock_enable_0 = VCC;
H1_ram_block[12][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[12][0]_PORT_A_address_reg, , , , , , H1_ram_block[12][0]_clock_0, , H1_ram_block[12][0]_clock_enable_0, , , );
H1_ram_block[12][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[12][0]_PORT_A_data_out, H1_ram_block[12][0]_clock_0, , , H1_ram_block[12][0]_clock_enable_0);
H1_ram_block[12][0] = H1_ram_block[12][0]_PORT_A_data_out_reg[0];


--K02L1 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00018|result_node~7 and unplaced
--operation mode is normal
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