filter.map.summary

来自「FPGA开发光盘各章节实例的设计工程与源码」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Mon Dec 10 15:43:55 2007
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : filter
Top-level Entity Name : filter
Family : Stratix
Total logic elements : 656
Total pins : 49
Total virtual pins : 0
Total memory bits : 1,048,576
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0