filter.fit.smsg

FPGA开发光盘各章节实例的设计工程与源码

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Dec 10 15:43:56 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off filter -c filter
Info: Selected device EP1S80F1508C7 for design "filter"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S40F1508C7 is compatible
    Info: Device EP1S60F1508C7 is compatible
    Info: Device EP1S80F1508I7 is compatible
Info: DATA[0] dual-purpose pin not reserved
Warning: No exact pin location assignment(s) for 49 pins of 49 total pins
    Info: Pin z[1] not assigned to an exact location on the device
    Info: Pin z[2] not assigned to an exact location on the device
    Info: Pin z[3] not assigned to an exact location on the device
    Info: Pin z[4] not assigned to an exact location on the device
    Info: Pin z[5] not assigned to an exact location on the device
    Info: Pin z[6] not assigned to an exact location on the device
    Info: Pin z[7] not assigned to an exact location on the device
    Info: Pin z[8] not assigned to an exact location on the device
    Info: Pin z[9] not assigned to an exact location on the device
    Info: Pin z[10] not assigned to an exact location on the device
    Info: Pin z[11] not assigned to an exact location on the device
    Info: Pin z[12] not assigned to an exact location on the device
    Info: Pin z[13] not assigned to an exact location on the device
    Info: Pin z[14] not assigned to an exact location on the device
    Info: Pin z[15] not assigned to an exact location on the device
    Info: Pin z[16] not assigned to an exact location on the device
    Info: Pin z[17] not assigned to an exact location on the device
    Info: Pin z[18] not assigned to an exact location on the device
    Info: Pin test_coefout[1] not assigned to an exact location on the device
    Info: Pin test_coefout[2] not assigned to an exact location on the device
    Info: Pin test_coefout[3] not assigned to an exact location on the device
    Info: Pin test_coefout[4] not assigned to an exact location on the device
    Info: Pin test_coefout[5] not assigned to an exact location on the device
    Info: Pin test_coefout[6] not assigned to an exact location on the device
    Info: Pin test_coefout[7] not assigned to an exact location on the device
    Info: Pin test_coefout[8] not assigned to an exact location on the device
    Info: Pin test_coefout[9] not assigned to an exact location on the device
    Info: Pin test_coefout[10] not assigned to an exact location on the device
    Info: Pin test_coefout[11] not assigned to an exact location on the device
    Info: Pin test_coefout[12] not assigned to an exact location on the device
    Info: Pin test_coefout[13] not assigned to an exact location on the device
    Info: Pin test_coefout[14] not assigned to an exact location on the device
    Info: Pin test_coefout[15] not assigned to an exact location on the device
    Info: Pin test_coefout[16] not assigned to an exact location on the device
    Info: Pin g_clk not assigned to an exact location on the device
    Info: Pin clr not assigned to an exact location on the device
    Info: Pin xin[1] not assigned to an exact location on the device
    Info: Pin ad_end not assigned to an exact location on the device
    Info: Pin xin[2] not assigned to an exact location on the device
    Info: Pin xin[3] not assigned to an exact location on the device
    Info: Pin xin[4] not assigned to an exact location on the device
    Info: Pin xin[5] not assigned to an exact location on the device
    Info: Pin xin[6] not assigned to an exact location on the device
    Info: Pin xin[7] not assigned to an exact location on the device
    Info: Pin xin[8] not assigned to an exact location on the device
    Info: Pin xin[9] not assigned to an exact location on the device
    Info: Pin xin[10] not assigned to an exact location on the device
    Info: Pin xin[11] not assigned to an exact location on the device
    Info: Pin xin[12] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "g_clk" to use Global clock in PIN AA35
Info: Automatically promoted signal "clr" to use Global clock in PIN Y37
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:01
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 47 (unused VREF, 3.30 VCCIO, 13 input, 34 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  148 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  150 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  141 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  150 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  150 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  150 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  151 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  141 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  4 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  4 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:27
Info: Estimated most critical path is memory to register delay of 8.902 ns
    Info: 1: + IC(0.000 ns) + CELL(0.090 ns) = 0.090 ns; Loc. = M4K_X73_Y76; Fanout = 1; MEM Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a144'
    Info: 2: + IC(2.166 ns) + CELL(0.381 ns) = 2.637 ns; Loc. = LAB_X68_Y52; Fanout = 1; COMB Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1157w~456'
    Info: 3: + IC(0.259 ns) + CELL(0.381 ns) = 3.277 ns; Loc. = LAB_X68_Y52; Fanout = 1; COMB Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1157w~458'
    Info: 4: + IC(0.113 ns) + CELL(0.527 ns) = 3.917 ns; Loc. = LAB_X68_Y52; Fanout = 2; COMB Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1157w~461'
    Info: 5: + IC(0.747 ns) + CELL(0.100 ns) = 4.764 ns; Loc. = LAB_X67_Y52; Fanout = 4; COMB Node = 'accumulator:shift_add|accum[2]~COMBOUT'
    Info: 6: + IC(1.188 ns) + CELL(0.509 ns) = 6.461 ns; Loc. = LAB_X59_Y52; Fanout = 2; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT'
    Info: 7: + IC(0.000 ns) + CELL(0.069 ns) = 6.530 ns; Loc. = LAB_X59_Y52; Fanout = 2; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT'
    Info: 8: + IC(0.000 ns) + CELL(0.069 ns) = 6.599 ns; Loc. = LAB_X59_Y52; Fanout = 2; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT'
    Info: 9: + IC(0.000 ns) + CELL(0.069 ns) = 6.668 ns; Loc. = LAB_X59_Y52; Fanout = 2; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT'
    Info: 10: + IC(0.000 ns) + CELL(0.251 ns) = 6.919 ns; Loc. = LAB_X59_Y52; Fanout = 6; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT'
    Info: 11: + IC(0.000 ns) + CELL(0.126 ns) = 7.045 ns; Loc. = LAB_X59_Y52; Fanout = 6; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT'
    Info: 12: + IC(0.000 ns) + CELL(0.566 ns) = 7.611 ns; Loc. = LAB_X59_Y51; Fanout = 1; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[14]'
    Info: 13: + IC(1.188 ns) + CELL(0.103 ns) = 8.902 ns; Loc. = LAB_X67_Y51; Fanout = 4; REG Node = 'accumulator:shift_add|accum[16]'
    Info: Total cell delay = 3.241 ns ( 36.41 % )
    Info: Total interconnect delay = 5.661 ns ( 63.59 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 6%
    Info: The peak interconnect region extends from location X57_Y46 to location X67_Y57
Info: Fitter routing operations ending: elapsed time is 00:00:21
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 452 megabytes of memory during processing
    Info: Processing ended: Mon Dec 10 15:46:00 2007
    Info: Elapsed time: 00:02:04