filter.tdf

FPGA开发光盘各章节实例的设计工程与源码

include "filter_shift";
include "p_s";
include "s_term";
include "filter_coef";
include "accumulator";
include "filter_con";


parameters
(
tap = 16,              --3,
x_wid = 12,
x_pre = 10,
coef_wid = 16,
coef_pre = 15,
z_wid = 18,
z_pre = coef_pre,

pipeline = "yes"
);

subdesign filter
(
	g_clk				:input;
	clr 				:input = vcc;
	ad_end				:input;-- = vcc;
	xin[x_wid..1]		:input;
	z[z_wid..1] 		:output;
	test_coefout[coef_wid..1]	:output;
)

variable
cont		: filter_con with (x_width = x_wid);

shift_reg	: filter_shift with(tap=tap,
								x_wid=x_wid
								);

p_s_c		: s_term with (in_width = x_wid,
						   term_wid = tap);

rom_coef	: filter_coef;  -- with (    addr_wid = tap,
						   --	    coef_wid = coef_wid,
							--        ini_file = "E:\w_fir\Quartus\wrom.mif");

shift_add	: accumulator with (x_width = coef_wid,
								x_pre = coef_pre,
								y_width = x_wid,
								y_pre = x_pre,
								pipeline = "yes",
								out_int = z_wid-z_pre,
								out_pre = z_pre
								);

--clk	: node;

begin
	--clk = global(g_clk);
	
	cont.clk = g_clk;																							
	cont.clr = clr;
	cont.ad_end = ad_end;
	
	shift_reg.clk = g_clk;
	shift_reg.clr = clr;
	shift_reg.xin[] = xin[];
	shift_reg.s_en = cont.shifter_en;

	p_s_c.clk = g_clk;
	p_s_c.clr = clr;
	p_s_c.load = cont.ps_load;
	p_s_c.data_in[][] = shift_reg.y_ff[][];
	
    rom_coef.clock = g_clk;
	rom_coef.address[] = p_s_c.rom_ad[];
	
	shift_add.clk = g_clk;	
	shift_add.clr = clr;
	shift_add.a_load = cont.add_load;
	shift_add.add_sub = cont.add_sub;
	shift_add.f_en = cont.flip_en;		
	shift_add.datain[] = rom_coef.q[];		
	
	z[] = shift_add.dataout[];
	test_coefout[coef_wid..1]=rom_coef.q[];
end;