filter_shift.tdf

FPGA开发光盘各章节实例的设计工程与源码

parameters
(
		tap=16,
		x_wid=12           --3
);
subdesign filter_shift
(
 clk				: input;
 clr				: input = vcc;
 xin[x_wid..1]		: input;
 s_en				: input;-- = gnd;
 y_ff[tap..1][x_wid..1]:output;
)

variable
	shifter_ff[tap..1][x_wid..1]	: dffe;
	
begin
	shifter_ff[][].clrn = clr;
	shifter_ff[][].clk = clk;
	shifter_ff[][].ena = s_en;
	shifter_ff[1][].d = xin[];	
	for i in 2 to tap generate
	 shifter_ff[i][].d = shifter_ff[i-1][].q;
	end generate;
	for i in 1 to tap generate
	 y_ff[i][] = shifter_ff[i][].q;
	end generate;
end;