absthet_core.xco

FPGA开发光盘各章节实例的设计工程与源码

# Xilinx CORE Generator 6.1.03i
# Username = administrator
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = E:\51sh\sh4
# ExpandedProjectPath = E:\51sh\sh4
# OverwriteFiles = true
# Core name: absthet_core
# Number of Primitives in design: 1299
# Number of CLBs used in design: 62
# Number of Slices used in design: 229
# Number of LUT sites used in design: 368
# Number of LUTs used in design: 357
# Number of REG used in design: 390
# Number of SRL16s used in design: 11
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 1
# Huset "absthet_core/top/c1/cm_top" = (0, 0) to (16, 4) in CLBs
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET XilinxFamily = Virtex2
SET OutputOption = OutputProducts
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SET OutputProducts = ImpNetlist ASYSymbol VHDLSim VerilogSim
SELECT CORDIC Virtex2 Xilinx,_Inc. 2.0
CSET synchronization_enable = No_Override
CSET create_rpm = true
CSET register_inputs = true
CSET sclr = false
CSET architectural_configuration = Parallel
CSET phase_format = Radians
CSET nd = false
CSET data_format = SignedFraction
CSET register_outputs = true
CSET rdy = false
CSET aclr = false
CSET ce = false
CSET y_out = false
CSET component_name = absthet_core
CSET pipelining_mode = Maximum
CSET compensation_scaling = No_Scale_Compensation
CSET input_width = 8
CSET round_mode = Nearest_Even
CSET iterations = 0
CSET precision = 0
CSET functional_selection = Translate
CSET output_width = 8
CSET phase_output = true
CSET x_out = true
CSET coarse_rotation = true
GENERATE