top_sh3.sch

FPGA开发光盘各章节实例的设计工程与源码

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "virtex2"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL xr2(7:0)
        SIGNAL wi(7:0)
        SIGNAL xi2(7:0)
        SIGNAL clock
        BEGIN SIGNAL mulout1(15:0)
        END SIGNAL
        BEGIN SIGNAL mulout2(15:0)
        END SIGNAL
        SIGNAL XLXN_13(15:0)
        SIGNAL XLXN_14(15:0)
        BEGIN SIGNAL indiv2out(7:0)
        END SIGNAL
        SIGNAL XLXN_28(15:0)
        BEGIN SIGNAL sub1out(15:0)
        END SIGNAL
        BEGIN SIGNAL contr2out(7:0)
        END SIGNAL
        SIGNAL XLXN_39(7:0)
        SIGNAL XLXN_41(7:0)
        SIGNAL xkr1(7:0)
        SIGNAL xkr2(7:0)
        SIGNAL xki1(7:0)
        SIGNAL xki2(7:0)
        SIGNAL xr1(7:0)
        SIGNAL xi1(7:0)
        SIGNAL wr(7:0)
        PORT Input xr2(7:0)
        PORT Input wi(7:0)
        PORT Input xi2(7:0)
        PORT Input clock
        PORT Output xkr1(7:0)
        PORT Output xkr2(7:0)
        PORT Output xki1(7:0)
        PORT Output xki2(7:0)
        PORT Input xr1(7:0)
        PORT Input xi1(7:0)
        PORT Input wr(7:0)
        BEGIN BLOCKDEF core_mul8clk
            TIMESTAMP 2004 4 27 1 52 40
            RECTANGLE N 32 0 256 320 
            BEGIN LINE W 0 48 32 48 
            END LINE
            BEGIN LINE W 0 112 32 112 
            END LINE
            LINE N 0 272 32 272 
            BEGIN LINE W 256 80 288 80 
            END LINE
        END BLOCKDEF
        BEGIN BLOCKDEF core_sub16clk
            TIMESTAMP 2004 4 27 1 42 53
            RECTANGLE N 32 0 448 384 
            BEGIN LINE W 0 176 32 176 
            END LINE
            BEGIN LINE W 0 80 32 80 
            END LINE
            LINE N 0 336 32 336 
            BEGIN LINE W 448 272 480 272 
            END LINE
        END BLOCKDEF
        BEGIN BLOCKDEF core_add16clk
            TIMESTAMP 2004 4 27 1 42 12
            RECTANGLE N 32 0 448 384 
            BEGIN LINE W 0 176 32 176 
            END LINE
            BEGIN LINE W 0 80 32 80 
            END LINE
            LINE N 0 336 32 336 
            BEGIN LINE W 448 272 480 272 
            END LINE
        END BLOCKDEF
        BEGIN BLOCKDEF core_add8clk
            TIMESTAMP 2004 4 27 1 42 23
            RECTANGLE N 32 0 448 384 
            BEGIN LINE W 0 176 32 176 
            END LINE
            BEGIN LINE W 0 80 32 80 
            END LINE
            LINE N 0 336 32 336 
            BEGIN LINE W 448 272 480 272 
            END LINE
        END BLOCKDEF
        BEGIN BLOCKDEF core_sub8clk
            TIMESTAMP 2004 4 27 1 43 3
            RECTANGLE N 32 0 448 384 
            BEGIN LINE W 0 176 32 176 
            END LINE
            BEGIN LINE W 0 80 32 80 
            END LINE
            LINE N 0 336 32 336 
            BEGIN LINE W 448 272 480 272 
            END LINE
        END BLOCKDEF
        BEGIN BLOCKDEF indat_div2
            TIMESTAMP 2004 4 27 3 27 24
            RECTANGLE N 64 -128 320 0 
            RECTANGLE N 320 -68 384 -40 
            LINE N 64 -72 0 -72 
            RECTANGLE N 0 -84 64 -60 
            LINE N 64 -24 0 -24 
            LINE N 320 -52 384 -52 
        END BLOCKDEF
        BEGIN BLOCKDEF contract2
            TIMESTAMP 2004 4 27 3 49 28
            RECTANGLE N 64 -128 320 0 
            LINE N 64 -96 0 -96 
            LINE N 64 -32 0 -32 
            RECTANGLE N 0 -44 64 -20 
            LINE N 320 -96 384 -96 
            RECTANGLE N 320 -108 384 -84 
        END BLOCKDEF
        BEGIN BLOCK XLXI_1 core_mul8clk
            PIN a(7:0) xr2(7:0)
            PIN b(7:0) wr(7:0)
            PIN clk clock
            PIN q(15:0) mulout1(15:0)
        END BLOCK
        BEGIN BLOCK XLXI_2 core_mul8clk
            PIN a(7:0) xi2(7:0)
            PIN b(7:0) wi(7:0)
            PIN clk clock
            PIN q(15:0) mulout2(15:0)
        END BLOCK
        BEGIN BLOCK XLXI_3 core_mul8clk
            PIN a(7:0) xr2(7:0)
            PIN b(7:0) wi(7:0)
            PIN clk clock
            PIN q(15:0) XLXN_13(15:0)
        END BLOCK
        BEGIN BLOCK XLXI_4 core_mul8clk
            PIN a(7:0) xi2(7:0)
            PIN b(7:0) wr(7:0)
            PIN clk clock
            PIN q(15:0) XLXN_14(15:0)
        END BLOCK
        BEGIN BLOCK XLXI_9 core_sub16clk
            PIN B(15:0) mulout2(15:0)
            PIN A(15:0) mulout1(15:0)
            PIN CLK clock
            PIN Q(15:0) sub1out(15:0)
        END BLOCK
        BEGIN BLOCK XLXI_10 core_add16clk
            PIN B(15:0) XLXN_14(15:0)
            PIN A(15:0) XLXN_13(15:0)
            PIN CLK clock
            PIN Q(15:0) XLXN_28(15:0)
        END BLOCK
        BEGIN BLOCK XLXI_11 core_add8clk
            PIN B(7:0) contr2out(7:0)
            PIN A(7:0) indiv2out(7:0)
            PIN CLK clock
            PIN Q(7:0) xkr1(7:0)
        END BLOCK
        BEGIN BLOCK XLXI_13 core_sub8clk
            PIN B(7:0) contr2out(7:0)
            PIN A(7:0) indiv2out(7:0)
            PIN CLK clock
            PIN Q(7:0) xkr2(7:0)
        END BLOCK
        BEGIN BLOCK XLXI_12 core_add8clk
            PIN B(7:0) XLXN_41(7:0)
            PIN A(7:0) XLXN_39(7:0)
            PIN CLK clock
            PIN Q(7:0) xki1(7:0)
        END BLOCK
        BEGIN BLOCK XLXI_19 indat_div2
            PIN outdat_x(7:0) indiv2out(7:0)
            PIN indat_xri(7:0) xr1(7:0)
            PIN clk clock
        END BLOCK
        BEGIN BLOCK XLXI_14 core_sub8clk
            PIN B(7:0) XLXN_41(7:0)
            PIN A(7:0) XLXN_39(7:0)
            PIN CLK clock
            PIN Q(7:0) xki2(7:0)
        END BLOCK
        BEGIN BLOCK XLXI_20 indat_div2
            PIN outdat_x(7:0) XLXN_39(7:0)
            PIN indat_xri(7:0) xi1(7:0)
            PIN clk clock
        END BLOCK
        BEGIN BLOCK XLXI_21 contract2
            PIN clk clock
            PIN indat_mulout(15:0) sub1out(15:0)
            PIN outdat_temp(7:0) contr2out(7:0)
        END BLOCK
        BEGIN BLOCK XLXI_22 contract2
            PIN clk clock
            PIN indat_mulout(15:0) XLXN_28(15:0)
            PIN outdat_temp(7:0) XLXN_41(7:0)
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        BEGIN INSTANCE XLXI_1 672 608 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_2 672 992 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_3 672 1376 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_4 672 1760 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_9 1088 784 R0
        END INSTANCE
        BEGIN BRANCH wr(7:0)
            WIRE 432 1968 576 1968
            WIRE 576 720 672 720
            WIRE 576 720 576 1872
            WIRE 576 1872 672 1872
            WIRE 576 1872 576 1968
        END BRANCH
        BEGIN BRANCH wi(7:0)
            WIRE 432 2048 608 2048
            WIRE 608 1104 672 1104
            WIRE 608 1104 608 1488
            WIRE 608 1488 672 1488
            WIRE 608 1488 608 2048
        END BRANCH
        BEGIN BRANCH xi2(7:0)
            WIRE 432 1808 512 1808
            WIRE 512 1808 672 1808
            WIRE 512 1040 672 1040
            WIRE 512 1040 512 1808
        END BRANCH
        BEGIN BRANCH mulout1(15:0)
            WIRE 960 688 1024 688
            WIRE 1024 688 1024 864
            WIRE 1024 864 1088 864
        END BRANCH
        BEGIN BRANCH mulout2(15:0)
            WIRE 960 1072 1024 1072
            WIRE 1024 960 1024 1072
            WIRE 1024 960 1088 960
        END BRANCH
        BEGIN BRANCH XLXN_13(15:0)
            WIRE 960 1456 976 1456
            WIRE 976 1456 976 1552
            WIRE 976 1552 1088 1552
        END BRANCH
        BEGIN BRANCH XLXN_14(15:0)
            WIRE 960 1840 976 1840
            WIRE 976 1648 1088 1648
            WIRE 976 1648 976 1840
        END BRANCH
        IOMARKER 432 1808 xi2(7:0) R180 28
        BEGIN INSTANCE XLXI_11 2272 352 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_13 2272 896 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_12 2272 1408 R0
        END INSTANCE
        BEGIN BRANCH indiv2out(7:0)
            WIRE 2096 432 2208 432
            WIRE 2208 432 2272 432
            WIRE 2208 432 2208 976
            WIRE 2208 976 2272 976
        END BRANCH
        BEGIN INSTANCE XLXI_19 1712 480 R0
        END INSTANCE
        IOMARKER 416 2192 clock R180 28
        BEGIN INSTANCE XLXI_14 2272 1856 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_22 1728 1776 R0
        END INSTANCE
        BEGIN BRANCH XLXN_28(15:0)
            WIRE 1568 1744 1728 1744
        END BRANCH
        BEGIN INSTANCE XLXI_10 1088 1472 R0
        END INSTANCE
        BEGIN BRANCH XLXN_39(7:0)
            WIRE 2096 1936 2208 1936
            WIRE 2208 1936 2272 1936
            WIRE 2208 1488 2272 1488
            WIRE 2208 1488 2208 1936
        END BRANCH
        BEGIN BRANCH XLXN_41(7:0)
            WIRE 2112 1680 2176 1680
            WIRE 2176 1680 2176 2032
            WIRE 2176 2032 2272 2032
            WIRE 2176 1584 2176 1680
            WIRE 2176 1584 2272 1584
        END BRANCH
        BEGIN BRANCH contr2out(7:0)
            WIRE 2096 992 2176 992
            WIRE 2176 992 2176 1072
            WIRE 2176 1072 2272 1072
            WIRE 2176 528 2272 528
            WIRE 2176 528 2176 800
            WIRE 2176 800 2176 992
        END BRANCH
        BEGIN BRANCH sub1out(15:0)
            WIRE 1568 1056 1632 1056
            WIRE 1632 1056 1712 1056
        END BRANCH
        BEGIN BRANCH clock
            WIRE 416 2192 656 2192
            WIRE 656 2192 1056 2192
            WIRE 1056 2192 1680 2192
            WIRE 1680 2192 2240 2192
            WIRE 2240 2192 2272 2192
            WIRE 656 464 656 880
            WIRE 656 880 656 1264
            WIRE 656 1264 672 1264
            WIRE 656 1264 656 1648
            WIRE 656 1648 672 1648
            WIRE 656 1648 656 2032
            WIRE 656 2032 672 2032
            WIRE 656 2032 656 2192
            WIRE 656 880 672 880
            WIRE 656 464 1632 464
            WIRE 1632 464 1712 464
            WIRE 1632 464 1632 992
            WIRE 1632 992 1712 992
            WIRE 1056 1120 1088 1120
            WIRE 1056 1120 1056 1808
            WIRE 1056 1808 1088 1808
            WIRE 1056 1808 1056 2192
            WIRE 1680 1680 1728 1680
            WIRE 1680 1680 1680 1968
            WIRE 1680 1968 1680 2192
            WIRE 1680 1968 1712 1968
            WIRE 2240 688 2272 688
            WIRE 2240 688 2240 1232
            WIRE 2240 1232 2272 1232
            WIRE 2240 1232 2240 1744
            WIRE 2240 1744 2240 2192
            WIRE 2240 1744 2272 1744
        END BRANCH
        BEGIN INSTANCE XLXI_21 1712 1088 R0
        END INSTANCE
        BEGIN INSTANCE XLXI_20 1712 1984 R0
        END INSTANCE
        BEGIN BRANCH xkr1(7:0)
            WIRE 2752 624 2864 624
        END BRANCH
        BEGIN BRANCH xkr2(7:0)
            WIRE 2752 1168 2864 1168
        END BRANCH
        BEGIN BRANCH xki1(7:0)
            WIRE 2752 1680 2864 1680
        END BRANCH
        BEGIN BRANCH xki2(7:0)
            WIRE 2752 2128 2864 2128
        END BRANCH
        IOMARKER 2864 624 xkr1(7:0) R0 28
        IOMARKER 2864 1168 xkr2(7:0) R0 28
        IOMARKER 2864 1680 xki1(7:0) R0 28
        IOMARKER 2864 2128 xki2(7:0) R0 28
        IOMARKER 432 2048 wi(7:0) R180 28
        BEGIN BRANCH xr1(7:0)
            WIRE 432 656 560 656
            WIRE 560 400 1712 400
            WIRE 560 400 560 656
        END BRANCH
        IOMARKER 432 656 xr1(7:0) R180 28
        BEGIN BRANCH xi1(7:0)
            WIRE 448 1344 544 1344
            WIRE 544 1344 544 2128
            WIRE 544 2128 1536 2128
            WIRE 1536 1904 1536 2128
            WIRE 1536 1904 1696 1904
            WIRE 1696 1904 1712 1904
        END BRANCH
        IOMARKER 448 1344 xi1(7:0) R180 28
        BEGIN BRANCH xr2(7:0)
            WIRE 416 960 640 960
            WIRE 640 960 640 1424
            WIRE 640 1424 672 1424
            WIRE 640 656 672 656
            WIRE 640 656 640 960
        END BRANCH
        IOMARKER 416 960 xr2(7:0) R180 28
        IOMARKER 432 1968 wr(7:0) R180 28
    END SHEET
END SCHEMATIC