core_sub16clk.vhd

FPGA开发光盘各章节实例的设计工程与源码

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-- You must compile the wrapper file core_sub16clk.vhd when simulating
-- the core, core_sub16clk. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY core_sub16clk IS
	port (
	A: IN std_logic_VECTOR(15 downto 0);
	B: IN std_logic_VECTOR(15 downto 0);
	Q: OUT std_logic_VECTOR(15 downto 0);
	CLK: IN std_logic);
END core_sub16clk;

ARCHITECTURE core_sub16clk_a OF core_sub16clk IS

component wrapped_core_sub16clk
	port (
	A: IN std_logic_VECTOR(15 downto 0);
	B: IN std_logic_VECTOR(15 downto 0);
	Q: OUT std_logic_VECTOR(15 downto 0);
	CLK: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_core_sub16clk use entity XilinxCoreLib.C_ADDSUB_V6_0(behavioral)
		generic map(
			c_has_bypass_with_cin => 0,
			c_a_type => 0,
			c_has_sclr => 0,
			c_has_b_out => 0,
			c_sync_priority => 1,
			c_has_aset => 0,
			c_has_s => 0,
			c_has_q => 1,
			c_bypass_enable => 0,
			c_b_constant => 0,
			c_has_ovfl => 0,
			c_high_bit => 15,
			c_latency => 1,
			c_sinit_val => "0",
			c_has_bypass => 0,
			c_pipe_stages => 1,
			c_has_sset => 0,
			c_has_ainit => 0,
			c_has_a_signed => 0,
			c_has_q_c_out => 0,
			c_b_type => 0,
			c_has_add => 0,
			c_has_sinit => 0,
			c_has_b_in => 0,
			c_has_b_signed => 0,
			c_bypass_low => 0,
			c_b_value => "0",
			c_enable_rlocs => 1,
			c_add_mode => 1,
			c_has_aclr => 0,
			c_out_width => 16,
			c_low_bit => 0,
			c_ainit_val => "0000",
			c_has_q_ovfl => 0,
			c_has_q_b_out => 0,
			c_has_c_out => 0,
			c_b_width => 16,
			c_a_width => 16,
			c_sync_enable => 0,
			c_has_ce => 0,
			c_has_c_in => 0);
BEGIN

U0 : wrapped_core_sub16clk
		port map (
			A => A,
			B => B,
			Q => Q,
			CLK => CLK);
END core_sub16clk_a;

-- synopsys translate_on