contract2.vhd

FPGA开发光盘各章节实例的设计工程与源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity contract2 is
  port(
			indat_mulout   : in  std_logic_vector(15 downto 0);
  			clk			   : in  std_logic;
		   outdat_temp    : out std_logic_vector(7 downto 0)	
		);
end contract2;

architecture rtl of contract2 is
begin
  process(clk,indat_mulout)
   begin
	  if (clk'event and clk='1')then
	     outdat_temp<=indat_mulout(15)&indat_mulout(15 downto 9);		
     end if;
   end process;
end rtl;