top_sh3_timesim.vhd

FPGA开发光盘各章节实例的设计工程与源码

  signal xki1_7_ENABLE : STD_LOGIC; 
  signal xki1_7_GTS_OR_T : STD_LOGIC; 
  signal xki1_7_O : STD_LOGIC; 
  signal XLXI_3_N206_FFX_RST : STD_LOGIC; 
  signal xki2_4_ENABLE : STD_LOGIC; 
  signal xki2_4_GTS_OR_T : STD_LOGIC; 
  signal xki2_4_O : STD_LOGIC; 
  signal xki2_5_ENABLE : STD_LOGIC; 
  signal xki2_5_GTS_OR_T : STD_LOGIC; 
  signal xki2_5_O : STD_LOGIC; 
  signal xki2_6_ENABLE : STD_LOGIC; 
  signal xki2_6_GTS_OR_T : STD_LOGIC; 
  signal xki2_6_O : STD_LOGIC; 
  signal xki2_7_ENABLE : STD_LOGIC; 
  signal xki2_7_GTS_OR_T : STD_LOGIC; 
  signal xki2_7_O : STD_LOGIC; 
  signal sub1out_10_ENABLE : STD_LOGIC; 
  signal sub1out_10_GTS_OR_T : STD_LOGIC; 
  signal sub1out_10_O : STD_LOGIC; 
  signal sub1out_11_ENABLE : STD_LOGIC; 
  signal sub1out_11_GTS_OR_T : STD_LOGIC; 
  signal sub1out_11_O : STD_LOGIC; 
  signal sub1out_12_ENABLE : STD_LOGIC; 
  signal sub1out_12_GTS_OR_T : STD_LOGIC; 
  signal sub1out_12_O : STD_LOGIC; 
  signal sub1out_13_ENABLE : STD_LOGIC; 
  signal sub1out_13_GTS_OR_T : STD_LOGIC; 
  signal sub1out_13_O : STD_LOGIC; 
  signal sub1out_14_ENABLE : STD_LOGIC; 
  signal sub1out_14_GTS_OR_T : STD_LOGIC; 
  signal sub1out_14_O : STD_LOGIC; 
  signal XLXI_3_N217_FFY_RST : STD_LOGIC; 
  signal sub1out_15_ENABLE : STD_LOGIC; 
  signal sub1out_15_GTS_OR_T : STD_LOGIC; 
  signal sub1out_15_O : STD_LOGIC; 
  signal xkr1_0_ENABLE : STD_LOGIC; 
  signal xkr1_0_GTS_OR_T : STD_LOGIC; 
  signal xkr1_0_O : STD_LOGIC; 
  signal xkr1_1_ENABLE : STD_LOGIC; 
  signal xkr1_1_GTS_OR_T : STD_LOGIC; 
  signal xkr1_1_O : STD_LOGIC; 
  signal xkr1_2_ENABLE : STD_LOGIC; 
  signal xkr1_2_GTS_OR_T : STD_LOGIC; 
  signal xkr1_2_O : STD_LOGIC; 
  signal xkr1_3_ENABLE : STD_LOGIC; 
  signal xkr1_3_GTS_OR_T : STD_LOGIC; 
  signal xkr1_3_O : STD_LOGIC; 
  signal xkr2_0_ENABLE : STD_LOGIC; 
  signal xkr2_0_GTS_OR_T : STD_LOGIC; 
  signal xkr2_0_O : STD_LOGIC; 
  signal xkr1_4_ENABLE : STD_LOGIC; 
  signal xkr1_4_GTS_OR_T : STD_LOGIC; 
  signal xkr1_4_O : STD_LOGIC; 
  signal xkr2_1_ENABLE : STD_LOGIC; 
  signal xkr2_1_GTS_OR_T : STD_LOGIC; 
  signal xkr2_1_O : STD_LOGIC; 
  signal xkr1_5_ENABLE : STD_LOGIC; 
  signal xkr1_5_GTS_OR_T : STD_LOGIC; 
  signal xkr1_5_O : STD_LOGIC; 
  signal xkr2_2_ENABLE : STD_LOGIC; 
  signal xkr2_2_GTS_OR_T : STD_LOGIC; 
  signal xkr2_2_O : STD_LOGIC; 
  signal xkr1_6_ENABLE : STD_LOGIC; 
  signal xkr1_6_GTS_OR_T : STD_LOGIC; 
  signal xkr1_6_O : STD_LOGIC; 
  signal xkr2_3_ENABLE : STD_LOGIC; 
  signal xkr2_3_GTS_OR_T : STD_LOGIC; 
  signal xkr2_3_O : STD_LOGIC; 
  signal XLXI_3_N217_FFX_RST : STD_LOGIC; 
  signal xkr1_7_ENABLE : STD_LOGIC; 
  signal xkr1_7_GTS_OR_T : STD_LOGIC; 
  signal xkr1_7_O : STD_LOGIC; 
  signal xkr2_4_ENABLE : STD_LOGIC; 
  signal xkr2_4_GTS_OR_T : STD_LOGIC; 
  signal xkr2_4_O : STD_LOGIC; 
  signal xkr2_5_ENABLE : STD_LOGIC; 
  signal xkr2_5_GTS_OR_T : STD_LOGIC; 
  signal xkr2_5_O : STD_LOGIC; 
  signal xkr2_6_ENABLE : STD_LOGIC; 
  signal xkr2_6_GTS_OR_T : STD_LOGIC; 
  signal xkr2_6_O : STD_LOGIC; 
  signal xkr2_7_ENABLE : STD_LOGIC; 
  signal xkr2_7_GTS_OR_T : STD_LOGIC; 
  signal xkr2_7_O : STD_LOGIC; 
  signal indiv2out_0_ENABLE : STD_LOGIC; 
  signal indiv2out_0_GTS_OR_T : STD_LOGIC; 
  signal indiv2out_0_O : STD_LOGIC; 
  signal indiv2out_1_ENABLE : STD_LOGIC; 
  signal indiv2out_1_GTS_OR_T : STD_LOGIC; 
  signal indiv2out_1_O : STD_LOGIC; 
  signal indiv2out_2_ENABLE : STD_LOGIC; 
  signal indiv2out_2_GTS_OR_T : STD_LOGIC; 
  signal indiv2out_2_O : STD_LOGIC; 
  signal indiv2out_3_ENABLE : STD_LOGIC; 
  signal indiv2out_3_GTS_OR_T : STD_LOGIC; 
  signal indiv2out_3_O : STD_LOGIC; 
  signal XLXI_3_N214_FFY_RST : STD_LOGIC; 
  signal indiv2out_4_ENABLE : STD_LOGIC; 
  signal indiv2out_4_GTS_OR_T : STD_LOGIC; 
  signal indiv2out_4_O : STD_LOGIC; 
  signal indiv2out_5_ENABLE : STD_LOGIC; 
  signal indiv2out_5_GTS_OR_T : STD_LOGIC; 
  signal indiv2out_5_O : STD_LOGIC; 
  signal indiv2out_6_ENABLE : STD_LOGIC; 
  signal indiv2out_6_GTS_OR_T : STD_LOGIC; 
  signal indiv2out_6_O : STD_LOGIC; 
  signal indiv2out_7_ENABLE : STD_LOGIC; 
  signal indiv2out_7_GTS_OR_T : STD_LOGIC; 
  signal indiv2out_7_O : STD_LOGIC; 
  signal clock_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal XLXI_22_outdat_temp_1_DXMUX : STD_LOGIC; 
  signal XLXI_22_outdat_temp_1_DYMUX : STD_LOGIC; 
  signal XLXI_22_outdat_temp_1_CLKINV : STD_LOGIC; 
  signal XLXI_22_outdat_temp_3_DXMUX : STD_LOGIC; 
  signal XLXI_22_outdat_temp_3_DYMUX : STD_LOGIC; 
  signal XLXI_22_outdat_temp_3_CLKINV : STD_LOGIC; 
  signal XLXI_22_outdat_temp_5_DXMUX : STD_LOGIC; 
  signal XLXI_22_outdat_temp_5_DYMUX : STD_LOGIC; 
  signal XLXI_22_outdat_temp_5_CLKINV : STD_LOGIC; 
  signal XLXI_22_outdat_temp_7_DYMUX : STD_LOGIC; 
  signal XLXI_22_outdat_temp_7_CLKINV : STD_LOGIC; 
  signal XLXI_20_indat2clk_2_DXMUX : STD_LOGIC; 
  signal XLXI_20_indat2clk_2_DYMUX : STD_LOGIC; 
  signal XLXI_20_indat2clk_2_CLKINV : STD_LOGIC; 
  signal XLXI_20_indat2clk_4_DXMUX : STD_LOGIC; 
  signal XLXI_20_indat2clk_4_DYMUX : STD_LOGIC; 
  signal XLXI_20_indat2clk_4_CLKINV : STD_LOGIC; 
  signal XLXI_20_indat2clk_6_DXMUX : STD_LOGIC; 
  signal XLXI_20_indat2clk_6_DYMUX : STD_LOGIC; 
  signal XLXI_20_indat2clk_6_CLKINV : STD_LOGIC; 
  signal XLXI_3_N214_FFX_RST : STD_LOGIC; 
  signal XLXI_20_indat2clk_7_DYMUX : STD_LOGIC; 
  signal XLXI_20_indat2clk_7_CLKINV : STD_LOGIC; 
  signal XLXI_20_outdat_x_1_DXMUX : STD_LOGIC; 
  signal XLXI_20_outdat_x_1_DYMUX : STD_LOGIC; 
  signal XLXI_20_outdat_x_1_CLKINV : STD_LOGIC; 
  signal XLXI_20_outdat_x_3_DXMUX : STD_LOGIC; 
  signal XLXI_20_outdat_x_3_DYMUX : STD_LOGIC; 
  signal XLXI_20_outdat_x_3_CLKINV : STD_LOGIC; 
  signal XLXI_20_outdat_x_5_DXMUX : STD_LOGIC; 
  signal XLXI_20_outdat_x_5_DYMUX : STD_LOGIC; 
  signal XLXI_20_outdat_x_5_CLKINV : STD_LOGIC; 
  signal XLXI_20_outdat_x_7_DYMUX : STD_LOGIC; 
  signal XLXI_20_outdat_x_7_CLKINV : STD_LOGIC; 
  signal XLXI_19_indat2clk_2_DXMUX : STD_LOGIC; 
  signal XLXI_19_indat2clk_2_DYMUX : STD_LOGIC; 
  signal XLXI_19_indat2clk_2_CLKINV : STD_LOGIC; 
  signal XLXI_19_indat2clk_4_DXMUX : STD_LOGIC; 
  signal XLXI_19_indat2clk_4_DYMUX : STD_LOGIC; 
  signal XLXI_19_indat2clk_4_CLKINV : STD_LOGIC; 
  signal XLXI_19_indat2clk_6_DXMUX : STD_LOGIC; 
  signal XLXI_19_indat2clk_6_DYMUX : STD_LOGIC; 
  signal XLXI_19_indat2clk_6_CLKINV : STD_LOGIC; 
  signal XLXI_19_indat2clk_7_DYMUX : STD_LOGIC; 
  signal XLXI_19_indat2clk_7_CLKINV : STD_LOGIC; 
  signal XLXI_3_N212_FFY_RST : STD_LOGIC; 
  signal XLXI_19_outdat_x_1_DXMUX : STD_LOGIC; 
  signal XLXI_19_outdat_x_1_DYMUX : STD_LOGIC; 
  signal XLXI_19_outdat_x_1_CLKINV : STD_LOGIC; 
  signal XLXI_19_outdat_x_3_DXMUX : STD_LOGIC; 
  signal XLXI_19_outdat_x_3_DYMUX : STD_LOGIC; 
  signal XLXI_19_outdat_x_3_CLKINV : STD_LOGIC; 
  signal XLXI_19_outdat_x_5_DXMUX : STD_LOGIC; 
  signal XLXI_19_outdat_x_5_DYMUX : STD_LOGIC; 
  signal XLXI_19_outdat_x_5_CLKINV : STD_LOGIC; 
  signal XLXI_21_outdat_temp_1_DXMUX : STD_LOGIC; 
  signal XLXI_21_outdat_temp_1_DYMUX : STD_LOGIC; 
  signal XLXI_21_outdat_temp_1_CLKINV : STD_LOGIC; 
  signal XLXI_19_outdat_x_7_DYMUX : STD_LOGIC; 
  signal XLXI_19_outdat_x_7_CLKINV : STD_LOGIC; 
  signal XLXI_21_outdat_temp_3_DXMUX : STD_LOGIC; 
  signal XLXI_21_outdat_temp_3_DYMUX : STD_LOGIC; 
  signal XLXI_21_outdat_temp_3_CLKINV : STD_LOGIC; 
  signal XLXI_21_outdat_temp_5_DXMUX : STD_LOGIC; 
  signal XLXI_21_outdat_temp_5_DYMUX : STD_LOGIC; 
  signal XLXI_21_outdat_temp_5_CLKINV : STD_LOGIC; 
  signal XLXI_21_outdat_temp_7_DYMUX : STD_LOGIC; 
  signal XLXI_21_outdat_temp_7_CLKINV : STD_LOGIC; 
  signal XLXI_3_N212_FFX_RST : STD_LOGIC; 
  signal XLXI_3_N210_FFY_RST : STD_LOGIC; 
  signal XLXI_3_N210_FFX_RST : STD_LOGIC; 
  signal XLXI_3_N204_FFY_RST : STD_LOGIC; 
  signal XLXI_2_N204_FFY_RST : STD_LOGIC; 
  signal XLXI_2_N204_FFX_RST : STD_LOGIC; 
  signal XLXI_2_N202_FFY_RST : STD_LOGIC; 
  signal XLXI_2_N202_FFX_RST : STD_LOGIC; 
  signal XLXI_1_N209_FFY_RST : STD_LOGIC; 
  signal XLXI_1_N209_FFX_RST : STD_LOGIC; 
  signal XLXI_1_N206_FFY_RST : STD_LOGIC; 
  signal XLXN_28_14_FFX_RST : STD_LOGIC; 
  signal xkr1_0_OBUF_FFY_RST : STD_LOGIC; 
  signal xkr1_0_OBUF_FFX_RST : STD_LOGIC; 
  signal xkr1_2_OBUF_FFY_RST : STD_LOGIC; 
  signal XLXI_1_N206_FFX_RST : STD_LOGIC; 
  signal XLXI_1_N217_FFY_RST : STD_LOGIC; 
  signal XLXI_1_N217_FFX_RST : STD_LOGIC; 
  signal XLXI_1_N214_FFY_RST : STD_LOGIC; 
  signal XLXI_1_N214_FFX_RST : STD_LOGIC; 
  signal XLXI_1_N212_FFY_RST : STD_LOGIC; 
  signal XLXI_1_N212_FFX_RST : STD_LOGIC; 
  signal XLXI_1_N210_FFY_RST : STD_LOGIC; 
  signal XLXI_1_N210_FFX_RST : STD_LOGIC; 
  signal XLXI_1_N204_FFY_RST : STD_LOGIC; 
  signal XLXI_1_N204_FFX_RST : STD_LOGIC; 
  signal XLXI_1_N202_FFY_RST : STD_LOGIC; 
  signal XLXI_1_N202_FFX_RST : STD_LOGIC; 
  signal sub1out_0_OBUF_FFY_RST : STD_LOGIC; 
  signal xki2_4_OBUF_FFY_RST : STD_LOGIC; 
  signal xki2_4_OBUF_FFX_RST : STD_LOGIC; 
  signal xki2_6_OBUF_FFY_RST : STD_LOGIC; 
  signal xi1_4_IFF_ICLK1INV : STD_LOGIC; 
  signal xi1_4_IFF_IFFDMUX : STD_LOGIC; 
  signal xi1_4_IFF_IFF1_RST : STD_LOGIC; 
  signal xi1_5_IFF_ICLK1INV : STD_LOGIC; 
  signal xi1_5_IFF_IFFDMUX : STD_LOGIC; 
  signal xi1_5_IFF_IFF1_RST : STD_LOGIC; 
  signal xi1_6_IFF_ICLK1INV : STD_LOGIC; 
  signal xi1_6_IFF_IFFDMUX : STD_LOGIC; 
  signal xi1_6_IFF_IFF1_RST : STD_LOGIC; 
  signal xki2_0_OBUF_FFX_RST : STD_LOGIC; 
  signal xki2_2_OBUF_FFY_RST : STD_LOGIC; 
  signal xki2_2_OBUF_FFX_RST : STD_LOGIC; 
  signal XLXI_22_outdat_temp_5_FFX_RST : STD_LOGIC; 
  signal XLXI_22_outdat_temp_7_FFY_RST : STD_LOGIC; 
  signal XLXI_20_indat2clk_2_FFY_RST : STD_LOGIC; 
  signal XLXI_20_indat2clk_2_FFX_RST : STD_LOGIC; 
  signal XLXI_20_indat2clk_4_FFY_RST : STD_LOGIC; 
  signal XLXI_20_indat2clk_4_FFX_RST : STD_LOGIC; 
  signal XLXI_20_indat2clk_6_FFY_RST : STD_LOGIC; 
  signal XLXI_20_indat2clk_6_FFX_RST : STD_LOGIC; 
  signal XLXI_20_indat2clk_7_FFY_RST : STD_LOGIC; 
  signal sub1out_0_OBUF_FFX_RST : STD_LOGIC; 
  signal sub1out_2_OBUF_FFY_RST : STD_LOGIC; 
  signal XLXI_3_N204_FFX_RST : STD_LOGIC; 
  signal XLXI_3_N202_FFY_RST : STD_LOGIC; 
  signal XLXI_3_N202_FFX_RST : STD_LOGIC; 
  signal XLXI_2_N209_FFY_RST : STD_LOGIC; 
  signal XLXI_2_N209_FFX_RST : STD_LOGIC; 
  signal XLXI_2_N206_FFY_RST : STD_LOGIC; 
  signal sub1out_6_OBUF_FFY_RST : STD_LOGIC; 
  signal sub1out_6_OBUF_FFX_RST : STD_LOGIC; 
  signal sub1out_8_OBUF_FFY_RST : STD_LOGIC; 
  signal XLXN_28_12_FFY_RST : STD_LOGIC; 
  signal XLXN_28_12_FFX_RST : STD_LOGIC; 
  signal XLXN_28_14_FFY_RST : STD_LOGIC; 
  signal XLXN_28_9_FFY_RST : STD_LOGIC; 
  signal sub1out_8_OBUF_FFX_RST : STD_LOGIC; 
  signal sub1out_10_OBUF_FFY_RST : STD_LOGIC; 
  signal sub1out_10_OBUF_FFX_RST : STD_LOGIC; 
  signal sub1out_14_OBUF_FFX_RST : STD_LOGIC; 
  signal xki1_0_OBUF_FFX_RST : STD_LOGIC; 
  signal xki1_2_OBUF_FFY_RST : STD_LOGIC; 
  signal xki1_2_OBUF_FFX_RST : STD_LOGIC; 
  signal xr1_7_IFF_ICLK1INV : STD_LOGIC; 
  signal xr1_7_IFF_IFFDMUX : STD_LOGIC; 
  signal xr1_7_IFF_IFF1_RST : STD_LOGIC; 
  signal xki1_4_OBUF_FFY_RST : STD_LOGIC; 
  signal xki1_4_OBUF_FFX_RST : STD_LOGIC; 
  signal xki1_6_OBUF_FFY_RST : STD_LOGIC; 
  signal xki1_6_OBUF_FFX_RST : STD_LOGIC; 
  signal xkr2_0_OBUF_FFY_RST : STD_LOGIC; 
  signal xkr2_0_OBUF_FFX_RST : STD_LOGIC; 
  signal xr1_4_IFF_ICLK1INV : STD_LOGIC; 
  signal xr1_4_IFF_IFFDMUX : STD_LOGIC; 
  signal xr1_4_IFF_IFF1_RST : STD_LOGIC; 
  signal xr1_5_IFF_ICLK1INV : STD_LOGIC; 
  signal xr1_5_IFF_IFFDMUX : STD_LOGIC; 
  signal xr1_5_IFF_IFF1_RST : STD_LOGIC; 
  signal xr1_6_IFF_ICLK1INV : STD_LOGIC; 
  signal xr1_6_IFF_IFFDMUX : STD_LOGIC; 
  signal xr1_6_IFF_IFF1_RST : STD_LOGIC; 
  signal XLXI_19_indat2clk_2_FFX_RST : STD_LOGIC; 
  signal XLXI_19_indat2clk_4_FFY_RST : STD_LOGIC; 
  signal XLXI_19_indat2clk_4_FFX_RST : STD_LOGIC; 
  signal XLXI_19_indat2clk_6_FFY_RST : STD_LOGIC; 
  signal XLXI_19_indat2clk_6_FFX_RST : STD_LOGIC; 
  signal XLXI_19_indat2clk_7_FFY_RST : STD_LOGIC; 
  signal XLXI_19_outdat_x_1_FFY_RST : STD_LOGIC; 
  signal XLXI_19_outdat_x_1_FFX_RST : STD_LOGIC; 
  signal xkr2_4_OBUF_FFX_RST : STD_LOGIC; 
  signal xkr2_6_OBUF_FFY_RST : STD_LOGIC; 
  signal xkr2_6_OBUF_FFX_RST : STD_LOGIC; 
  signal xki2_0_OBUF_FFY_RST : STD_LOGIC; 
  signal xkr2_2_OBUF_FFY_RST : STD_LOGIC; 
  signal xkr2_2_OBUF_FFX_RST : STD_LOGIC; 
  signal xkr2_4_OBUF_FFY_RST : STD_LOGIC; 
  signal xki2_6_OBUF_FFX_RST : STD_LOGIC; 
  signal xi1_1_IFF_ICLK1INV : STD_LOGIC; 
  signal xi1_1_IFF_IFFDMUX : STD_LOGIC; 
  signal xi1_1_IFF_IFF1_RST : STD_LOGIC; 
  signal xi1_2_IFF_ICLK1INV : STD_LOGIC; 
  signal xi1_2_IFF_IFFDMUX : STD_LOGIC; 
  signal xi1_2_IFF_IFF1_RST : STD_LOGIC; 
  signal xi1_3_IFF_ICLK1INV : STD_LOGIC; 
  signal xi1_3_IFF_IFFDMUX : STD_LOGIC; 
  signal xi1_3_IFF_IFF1_RST : STD_LOGIC; 
  signal XLXI_22_outdat_temp_1_FFY_RST : STD_LOGIC; 
  signal XLXI_22_outdat_temp_1_FFX_RST : STD_LOGIC; 
  signal XLXI_22_outdat_temp_3_FFY_RST : STD_LOGIC; 
  signal XLXI_22_outdat_temp_3_FFX_RST : STD_LOGIC; 
  signal XLXI_22_outdat_temp_5_FFY_RST : STD_LOGIC; 
  signal xr1_1_IFF_ICLK1INV : STD_LOGIC; 
  signal xr1_1_IFF_IFFDMUX : STD_LOGIC; 
  signal xr1_1_IFF_IFF1_RST : STD_LOGIC; 
  signal xr1_2_IFF_ICLK1INV : STD_LOGIC; 
  signal xr1_2_IFF_IFFDMUX : STD_LOGIC; 
  signal xr1_2_IFF_IFF1_RST : STD_LOGIC; 
  signal xr1_3_IFF_ICLK1INV : STD_LOGIC; 
  signal xr1_3_IFF_IFFDMUX : STD_LOGIC; 
  signal xr1_3_IFF_IFF1_RST : STD_LOGIC; 
  signal XLXI_20_outdat_x_1_FFY_RST : STD_LOGIC; 
  signal XLXI_20_outdat_x_1_FFX_RST : STD_LOGIC; 
  signal XLXI_20_outdat_x_3_FFY_RST : STD_LOGIC; 
  signal XLXI_20_outdat_x_3_FFX_RST : STD_LOGIC; 
  signal XLXI_20_outdat_x_5_FFY_RST : STD_LOGIC; 
  signal XLXI_20_outdat_x_5_FFX_RST : STD_LOGIC; 
  signal XLXI_20_outdat_x_7_FFY_RST : STD_LOGIC; 
  signal XLXI_19_indat2clk_2_FFY_RST : STD_LOGIC; 
  signal XLXI_21_outdat_temp_5_FFY_RST : STD_LOGIC; 
  signal XLXI_21_outdat_temp_5_FFX_RST : STD_LOGIC; 
  signal XLXI_21_outdat_temp_7_FFY_RST : STD_LOGIC; 
  signal XLXI_19_outdat_x_3_FFY_RST : STD_LOGIC; 
  signal XLXI_19_outdat_x_3_FFX_RST : STD_LOGIC; 
  signal XLXI_19_outdat_x_5_FFY_RST : STD_LOGIC; 
  signal XLXI_1