top_sh3_timesim.vhd

FPGA开发光盘各章节实例的设计工程与源码

  signal XLXI_13_N34 : STD_LOGIC; 
  signal xkr2_4_OBUF_DYMUX : STD_LOGIC; 
  signal xkr2_4_OBUF_XORG : STD_LOGIC; 
  signal XLXI_13_N37 : STD_LOGIC; 
  signal xkr2_4_OBUF_CYSELF : STD_LOGIC; 
  signal xkr2_4_OBUF_CYMUXFAST : STD_LOGIC; 
  signal xkr2_4_OBUF_CYAND : STD_LOGIC; 
  signal xkr2_4_OBUF_FASTCARRY : STD_LOGIC; 
  signal xkr2_4_OBUF_CYMUXG2 : STD_LOGIC; 
  signal xkr2_4_OBUF_CYMUXF2 : STD_LOGIC; 
  signal xkr2_4_OBUF_CY0G : STD_LOGIC; 
  signal xkr2_4_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_13_N40 : STD_LOGIC; 
  signal xkr2_4_OBUF_CLKINV : STD_LOGIC; 
  signal xkr2_6_OBUF_DXMUX : STD_LOGIC; 
  signal xkr2_6_OBUF_XORF : STD_LOGIC; 
  signal xkr2_6_OBUF_CYINIT : STD_LOGIC; 
  signal xkr2_6_OBUF_CY0F : STD_LOGIC; 
  signal xkr2_6_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_13_N46 : STD_LOGIC; 
  signal xkr2_6_OBUF_DYMUX : STD_LOGIC; 
  signal xkr2_6_OBUF_XORG : STD_LOGIC; 
  signal XLXI_13_N49 : STD_LOGIC; 
  signal XLXI_13_N52 : STD_LOGIC; 
  signal xkr2_6_OBUF_CLKINV : STD_LOGIC; 
  signal xki2_0_OBUF_DXMUX : STD_LOGIC; 
  signal xki2_0_OBUF_XORF : STD_LOGIC; 
  signal xki2_0_OBUF_CYINIT : STD_LOGIC; 
  signal xki2_0_OBUF_CY0F : STD_LOGIC; 
  signal xki2_0_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_14_N10 : STD_LOGIC; 
  signal xki2_0_OBUF_DYMUX : STD_LOGIC; 
  signal xki2_0_OBUF_XORG : STD_LOGIC; 
  signal xki2_0_OBUF_CYMUXG : STD_LOGIC; 
  signal XLXI_14_N13 : STD_LOGIC; 
  signal xki2_0_OBUF_CY0G : STD_LOGIC; 
  signal xki2_0_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_14_N16 : STD_LOGIC; 
  signal xki2_0_OBUF_CLKINV : STD_LOGIC; 
  signal xki2_2_OBUF_DXMUX : STD_LOGIC; 
  signal xki2_2_OBUF_XORF : STD_LOGIC; 
  signal xki2_2_OBUF_CYINIT : STD_LOGIC; 
  signal xki2_2_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_14_N22 : STD_LOGIC; 
  signal xki2_2_OBUF_DYMUX : STD_LOGIC; 
  signal xki2_2_OBUF_XORG : STD_LOGIC; 
  signal XLXI_14_N25 : STD_LOGIC; 
  signal xki2_2_OBUF_CYSELF : STD_LOGIC; 
  signal xki2_2_OBUF_CYMUXFAST : STD_LOGIC; 
  signal xki2_2_OBUF_CYAND : STD_LOGIC; 
  signal xki2_2_OBUF_FASTCARRY : STD_LOGIC; 
  signal xki2_2_OBUF_CYMUXG2 : STD_LOGIC; 
  signal xki2_2_OBUF_CYMUXF2 : STD_LOGIC; 
  signal xki2_2_OBUF_CY0G : STD_LOGIC; 
  signal xki2_2_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_14_N28 : STD_LOGIC; 
  signal xki2_2_OBUF_CLKINV : STD_LOGIC; 
  signal xki2_4_OBUF_DXMUX : STD_LOGIC; 
  signal xki2_4_OBUF_XORF : STD_LOGIC; 
  signal xki2_4_OBUF_CYINIT : STD_LOGIC; 
  signal xki2_4_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_14_N34 : STD_LOGIC; 
  signal xki2_4_OBUF_DYMUX : STD_LOGIC; 
  signal xki2_4_OBUF_XORG : STD_LOGIC; 
  signal XLXI_14_N37 : STD_LOGIC; 
  signal xki2_4_OBUF_CYSELF : STD_LOGIC; 
  signal xki2_4_OBUF_CYMUXFAST : STD_LOGIC; 
  signal xki2_4_OBUF_CYAND : STD_LOGIC; 
  signal xki2_4_OBUF_FASTCARRY : STD_LOGIC; 
  signal xki2_4_OBUF_CYMUXG2 : STD_LOGIC; 
  signal xki2_4_OBUF_CYMUXF2 : STD_LOGIC; 
  signal xki2_4_OBUF_CY0G : STD_LOGIC; 
  signal xki2_4_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_14_N40 : STD_LOGIC; 
  signal xki2_4_OBUF_CLKINV : STD_LOGIC; 
  signal xki2_6_OBUF_DXMUX : STD_LOGIC; 
  signal xki2_6_OBUF_XORF : STD_LOGIC; 
  signal xki2_6_OBUF_CYINIT : STD_LOGIC; 
  signal xki2_6_OBUF_CY0F : STD_LOGIC; 
  signal xki2_6_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_14_N46 : STD_LOGIC; 
  signal xki2_6_OBUF_DYMUX : STD_LOGIC; 
  signal xki2_6_OBUF_XORG : STD_LOGIC; 
  signal XLXI_14_N49 : STD_LOGIC; 
  signal XLXI_14_N52 : STD_LOGIC; 
  signal xki2_6_OBUF_CLKINV : STD_LOGIC; 
  signal mulout1_0_ENABLE : STD_LOGIC; 
  signal mulout1_0_GTS_OR_T : STD_LOGIC; 
  signal mulout1_0_O : STD_LOGIC; 
  signal mulout1_1_ENABLE : STD_LOGIC; 
  signal mulout1_1_GTS_OR_T : STD_LOGIC; 
  signal mulout1_1_O : STD_LOGIC; 
  signal mulout1_2_ENABLE : STD_LOGIC; 
  signal mulout1_2_GTS_OR_T : STD_LOGIC; 
  signal mulout1_2_O : STD_LOGIC; 
  signal XLXI_4_N210_FFX_RST : STD_LOGIC; 
  signal mulout1_3_ENABLE : STD_LOGIC; 
  signal mulout1_3_GTS_OR_T : STD_LOGIC; 
  signal mulout1_3_O : STD_LOGIC; 
  signal mulout2_0_ENABLE : STD_LOGIC; 
  signal mulout2_0_GTS_OR_T : STD_LOGIC; 
  signal mulout2_0_O : STD_LOGIC; 
  signal mulout1_4_ENABLE : STD_LOGIC; 
  signal mulout1_4_GTS_OR_T : STD_LOGIC; 
  signal mulout1_4_O : STD_LOGIC; 
  signal mulout2_1_ENABLE : STD_LOGIC; 
  signal mulout2_1_GTS_OR_T : STD_LOGIC; 
  signal mulout2_1_O : STD_LOGIC; 
  signal mulout1_5_ENABLE : STD_LOGIC; 
  signal mulout1_5_GTS_OR_T : STD_LOGIC; 
  signal mulout1_5_O : STD_LOGIC; 
  signal mulout2_2_ENABLE : STD_LOGIC; 
  signal mulout2_2_GTS_OR_T : STD_LOGIC; 
  signal mulout2_2_O : STD_LOGIC; 
  signal mulout1_6_ENABLE : STD_LOGIC; 
  signal mulout1_6_GTS_OR_T : STD_LOGIC; 
  signal mulout1_6_O : STD_LOGIC; 
  signal mulout2_3_ENABLE : STD_LOGIC; 
  signal mulout2_3_GTS_OR_T : STD_LOGIC; 
  signal mulout2_3_O : STD_LOGIC; 
  signal mulout1_7_ENABLE : STD_LOGIC; 
  signal mulout1_7_GTS_OR_T : STD_LOGIC; 
  signal mulout1_7_O : STD_LOGIC; 
  signal XLXI_4_N204_FFY_RST : STD_LOGIC; 
  signal mulout2_4_ENABLE : STD_LOGIC; 
  signal mulout2_4_GTS_OR_T : STD_LOGIC; 
  signal mulout2_4_O : STD_LOGIC; 
  signal mulout1_8_ENABLE : STD_LOGIC; 
  signal mulout1_8_GTS_OR_T : STD_LOGIC; 
  signal mulout1_8_O : STD_LOGIC; 
  signal mulout2_5_ENABLE : STD_LOGIC; 
  signal mulout2_5_GTS_OR_T : STD_LOGIC; 
  signal mulout2_5_O : STD_LOGIC; 
  signal mulout1_9_ENABLE : STD_LOGIC; 
  signal mulout1_9_GTS_OR_T : STD_LOGIC; 
  signal mulout1_9_O : STD_LOGIC; 
  signal mulout2_6_ENABLE : STD_LOGIC; 
  signal mulout2_6_GTS_OR_T : STD_LOGIC; 
  signal mulout2_6_O : STD_LOGIC; 
  signal mulout2_7_ENABLE : STD_LOGIC; 
  signal mulout2_7_GTS_OR_T : STD_LOGIC; 
  signal mulout2_7_O : STD_LOGIC; 
  signal mulout2_8_ENABLE : STD_LOGIC; 
  signal mulout2_8_GTS_OR_T : STD_LOGIC; 
  signal mulout2_8_O : STD_LOGIC; 
  signal mulout2_9_ENABLE : STD_LOGIC; 
  signal mulout2_9_GTS_OR_T : STD_LOGIC; 
  signal mulout2_9_O : STD_LOGIC; 
  signal wi_0_INBUF : STD_LOGIC; 
  signal wi_1_INBUF : STD_LOGIC; 
  signal wi_2_INBUF : STD_LOGIC; 
  signal wi_3_INBUF : STD_LOGIC; 
  signal XLXI_4_N204_FFX_RST : STD_LOGIC; 
  signal wi_4_INBUF : STD_LOGIC; 
  signal wi_5_INBUF : STD_LOGIC; 
  signal wi_6_INBUF : STD_LOGIC; 
  signal wi_7_INBUF : STD_LOGIC; 
  signal contr2out_0_ENABLE : STD_LOGIC; 
  signal contr2out_0_GTS_OR_T : STD_LOGIC; 
  signal contr2out_0_O : STD_LOGIC; 
  signal contr2out_1_ENABLE : STD_LOGIC; 
  signal contr2out_1_GTS_OR_T : STD_LOGIC; 
  signal contr2out_1_O : STD_LOGIC; 
  signal clock_INBUF : STD_LOGIC; 
  signal contr2out_2_ENABLE : STD_LOGIC; 
  signal contr2out_2_GTS_OR_T : STD_LOGIC; 
  signal contr2out_2_O : STD_LOGIC; 
  signal contr2out_3_ENABLE : STD_LOGIC; 
  signal contr2out_3_GTS_OR_T : STD_LOGIC; 
  signal contr2out_3_O : STD_LOGIC; 
  signal XLXI_4_N202_FFY_RST : STD_LOGIC; 
  signal contr2out_4_ENABLE : STD_LOGIC; 
  signal contr2out_4_GTS_OR_T : STD_LOGIC; 
  signal contr2out_4_O : STD_LOGIC; 
  signal contr2out_5_ENABLE : STD_LOGIC; 
  signal contr2out_5_GTS_OR_T : STD_LOGIC; 
  signal contr2out_5_O : STD_LOGIC; 
  signal mulout1_10_ENABLE : STD_LOGIC; 
  signal mulout1_10_GTS_OR_T : STD_LOGIC; 
  signal mulout1_10_O : STD_LOGIC; 
  signal contr2out_6_ENABLE : STD_LOGIC; 
  signal contr2out_6_GTS_OR_T : STD_LOGIC; 
  signal contr2out_6_O : STD_LOGIC; 
  signal mulout1_11_ENABLE : STD_LOGIC; 
  signal mulout1_11_GTS_OR_T : STD_LOGIC; 
  signal mulout1_11_O : STD_LOGIC; 
  signal contr2out_7_ENABLE : STD_LOGIC; 
  signal contr2out_7_GTS_OR_T : STD_LOGIC; 
  signal contr2out_7_O : STD_LOGIC; 
  signal mulout1_12_ENABLE : STD_LOGIC; 
  signal mulout1_12_GTS_OR_T : STD_LOGIC; 
  signal mulout1_12_O : STD_LOGIC; 
  signal mulout1_13_ENABLE : STD_LOGIC; 
  signal mulout1_13_GTS_OR_T : STD_LOGIC; 
  signal mulout1_13_O : STD_LOGIC; 
  signal mulout1_14_ENABLE : STD_LOGIC; 
  signal mulout1_14_GTS_OR_T : STD_LOGIC; 
  signal mulout1_14_O : STD_LOGIC; 
  signal wr_0_INBUF : STD_LOGIC; 
  signal mulout1_15_ENABLE : STD_LOGIC; 
  signal mulout1_15_GTS_OR_T : STD_LOGIC; 
  signal mulout1_15_O : STD_LOGIC; 
  signal wr_1_INBUF : STD_LOGIC; 
  signal XLXI_4_N202_FFX_RST : STD_LOGIC; 
  signal wr_2_INBUF : STD_LOGIC; 
  signal wr_3_INBUF : STD_LOGIC; 
  signal mulout2_10_ENABLE : STD_LOGIC; 
  signal mulout2_10_GTS_OR_T : STD_LOGIC; 
  signal mulout2_10_O : STD_LOGIC; 
  signal wr_4_INBUF : STD_LOGIC; 
  signal mulout2_11_ENABLE : STD_LOGIC; 
  signal mulout2_11_GTS_OR_T : STD_LOGIC; 
  signal mulout2_11_O : STD_LOGIC; 
  signal wr_5_INBUF : STD_LOGIC; 
  signal mulout2_12_ENABLE : STD_LOGIC; 
  signal mulout2_12_GTS_OR_T : STD_LOGIC; 
  signal mulout2_12_O : STD_LOGIC; 
  signal wr_6_INBUF : STD_LOGIC; 
  signal mulout2_13_ENABLE : STD_LOGIC; 
  signal mulout2_13_GTS_OR_T : STD_LOGIC; 
  signal mulout2_13_O : STD_LOGIC; 
  signal wr_7_INBUF : STD_LOGIC; 
  signal mulout2_14_ENABLE : STD_LOGIC; 
  signal mulout2_14_GTS_OR_T : STD_LOGIC; 
  signal mulout2_14_O : STD_LOGIC; 
  signal XLXI_3_N209_FFY_RST : STD_LOGIC; 
  signal mulout2_15_ENABLE : STD_LOGIC; 
  signal mulout2_15_GTS_OR_T : STD_LOGIC; 
  signal mulout2_15_O : STD_LOGIC; 
  signal xi1_1_INBUF : STD_LOGIC; 
  signal xi1_2_INBUF : STD_LOGIC; 
  signal xi1_3_INBUF : STD_LOGIC; 
  signal xi2_0_INBUF : STD_LOGIC; 
  signal xi1_4_INBUF : STD_LOGIC; 
  signal xi2_1_INBUF : STD_LOGIC; 
  signal xi1_5_INBUF : STD_LOGIC; 
  signal xi2_2_INBUF : STD_LOGIC; 
  signal xi1_6_INBUF : STD_LOGIC; 
  signal xi2_3_INBUF : STD_LOGIC; 
  signal xi1_7_IFF_IFF1_RST : STD_LOGIC; 
  signal xi1_7_IFF_IFFDMUX : STD_LOGIC; 
  signal xi1_7_IFF_ICLK1INV : STD_LOGIC; 
  signal xi1_7_INBUF : STD_LOGIC; 
  signal XLXI_3_N209_FFX_RST : STD_LOGIC; 
  signal sub1out_0_ENABLE : STD_LOGIC; 
  signal sub1out_0_GTS_OR_T : STD_LOGIC; 
  signal sub1out_0_O : STD_LOGIC; 
  signal xi2_4_INBUF : STD_LOGIC; 
  signal sub1out_1_ENABLE : STD_LOGIC; 
  signal sub1out_1_GTS_OR_T : STD_LOGIC; 
  signal sub1out_1_O : STD_LOGIC; 
  signal xi2_5_INBUF : STD_LOGIC; 
  signal sub1out_2_ENABLE : STD_LOGIC; 
  signal sub1out_2_GTS_OR_T : STD_LOGIC; 
  signal sub1out_2_O : STD_LOGIC; 
  signal xi2_6_INBUF : STD_LOGIC; 
  signal sub1out_3_ENABLE : STD_LOGIC; 
  signal sub1out_3_GTS_OR_T : STD_LOGIC; 
  signal sub1out_3_O : STD_LOGIC; 
  signal xi2_7_INBUF : STD_LOGIC; 
  signal sub1out_4_ENABLE : STD_LOGIC; 
  signal sub1out_4_GTS_OR_T : STD_LOGIC; 
  signal sub1out_4_O : STD_LOGIC; 
  signal XLXI_3_N206_FFY_RST : STD_LOGIC; 
  signal sub1out_5_ENABLE : STD_LOGIC; 
  signal sub1out_5_GTS_OR_T : STD_LOGIC; 
  signal sub1out_5_O : STD_LOGIC; 
  signal sub1out_6_ENABLE : STD_LOGIC; 
  signal sub1out_6_GTS_OR_T : STD_LOGIC; 
  signal sub1out_6_O : STD_LOGIC; 
  signal sub1out_7_ENABLE : STD_LOGIC; 
  signal sub1out_7_GTS_OR_T : STD_LOGIC; 
  signal sub1out_7_O : STD_LOGIC; 
  signal sub1out_8_ENABLE : STD_LOGIC; 
  signal sub1out_8_GTS_OR_T : STD_LOGIC; 
  signal sub1out_8_O : STD_LOGIC; 
  signal sub1out_9_ENABLE : STD_LOGIC; 
  signal sub1out_9_GTS_OR_T : STD_LOGIC; 
  signal sub1out_9_O : STD_LOGIC; 
  signal xr1_1_INBUF : STD_LOGIC; 
  signal xr1_2_INBUF : STD_LOGIC; 
  signal xr1_3_INBUF : STD_LOGIC; 
  signal xr2_0_INBUF : STD_LOGIC; 
  signal xr1_4_INBUF : STD_LOGIC; 
  signal xr2_1_INBUF : STD_LOGIC; 
  signal xr1_5_INBUF : STD_LOGIC; 
  signal xr2_2_INBUF : STD_LOGIC; 
  signal xr1_6_INBUF : STD_LOGIC; 
  signal xr2_3_INBUF : STD_LOGIC; 
  signal xr1_7_INBUF : STD_LOGIC; 
  signal xr2_4_INBUF : STD_LOGIC; 
  signal xr2_5_INBUF : STD_LOGIC; 
  signal xr2_6_INBUF : STD_LOGIC; 
  signal xr2_7_INBUF : STD_LOGIC; 
  signal xki1_0_ENABLE : STD_LOGIC; 
  signal xki1_0_GTS_OR_T : STD_LOGIC; 
  signal xki1_0_O : STD_LOGIC; 
  signal xki1_1_ENABLE : STD_LOGIC; 
  signal xki1_1_GTS_OR_T : STD_LOGIC; 
  signal xki1_1_O : STD_LOGIC; 
  signal xki1_2_ENABLE : STD_LOGIC; 
  signal xki1_2_GTS_OR_T : STD_LOGIC; 
  signal xki1_2_O : STD_LOGIC; 
  signal xki1_3_ENABLE : STD_LOGIC; 
  signal xki1_3_GTS_OR_T : STD_LOGIC; 
  signal xki1_3_O : STD_LOGIC; 
  signal xki2_0_ENABLE : STD_LOGIC; 
  signal xki2_0_GTS_OR_T : STD_LOGIC; 
  signal xki2_0_O : STD_LOGIC; 
  signal xki1_4_ENABLE : STD_LOGIC; 
  signal xki1_4_GTS_OR_T : STD_LOGIC; 
  signal xki1_4_O : STD_LOGIC; 
  signal xki2_1_ENABLE : STD_LOGIC; 
  signal xki2_1_GTS_OR_T : STD_LOGIC; 
  signal xki2_1_O : STD_LOGIC; 
  signal xki1_5_ENABLE : STD_LOGIC; 
  signal xki1_5_GTS_OR_T : STD_LOGIC; 
  signal xki1_5_O : STD_LOGIC; 
  signal xki2_2_ENABLE : STD_LOGIC; 
  signal xki2_2_GTS_OR_T : STD_LOGIC; 
  signal xki2_2_O : STD_LOGIC; 
  signal xki1_6_ENABLE : STD_LOGIC; 
  signal xki1_6_GTS_OR_T : STD_LOGIC; 
  signal xki1_6_O : STD_LOGIC; 
  signal xki2_3_ENABLE : STD_LOGIC; 
  signal xki2_3_GTS_OR_T : STD_LOGIC; 
  signal xki2_3_O : STD_LOGIC;