top_sh3_timesim.vhd

FPGA开发光盘各章节实例的设计工程与源码

  signal sub1out_8_OBUF_CLKINV : STD_LOGIC; 
  signal sub1out_10_OBUF_DXMUX : STD_LOGIC; 
  signal sub1out_10_OBUF_XORF : STD_LOGIC; 
  signal sub1out_10_OBUF_CYINIT : STD_LOGIC; 
  signal sub1out_10_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_9_N78 : STD_LOGIC; 
  signal sub1out_10_OBUF_DYMUX : STD_LOGIC; 
  signal sub1out_10_OBUF_XORG : STD_LOGIC; 
  signal XLXI_9_N81 : STD_LOGIC; 
  signal sub1out_10_OBUF_CYSELF : STD_LOGIC; 
  signal sub1out_10_OBUF_CYMUXFAST : STD_LOGIC; 
  signal sub1out_10_OBUF_CYAND : STD_LOGIC; 
  signal sub1out_10_OBUF_FASTCARRY : STD_LOGIC; 
  signal sub1out_10_OBUF_CYMUXG2 : STD_LOGIC; 
  signal sub1out_10_OBUF_CYMUXF2 : STD_LOGIC; 
  signal sub1out_10_OBUF_CY0G : STD_LOGIC; 
  signal sub1out_10_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_9_N84 : STD_LOGIC; 
  signal sub1out_10_OBUF_CLKINV : STD_LOGIC; 
  signal sub1out_12_OBUF_FFX_RST : STD_LOGIC; 
  signal sub1out_12_OBUF_FFY_RST : STD_LOGIC; 
  signal sub1out_12_OBUF_DXMUX : STD_LOGIC; 
  signal sub1out_12_OBUF_XORF : STD_LOGIC; 
  signal sub1out_12_OBUF_CYINIT : STD_LOGIC; 
  signal sub1out_12_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_9_N90 : STD_LOGIC; 
  signal sub1out_12_OBUF_DYMUX : STD_LOGIC; 
  signal sub1out_12_OBUF_XORG : STD_LOGIC; 
  signal XLXI_9_N93 : STD_LOGIC; 
  signal sub1out_12_OBUF_CYSELF : STD_LOGIC; 
  signal sub1out_12_OBUF_CYMUXFAST : STD_LOGIC; 
  signal sub1out_12_OBUF_CYAND : STD_LOGIC; 
  signal sub1out_12_OBUF_FASTCARRY : STD_LOGIC; 
  signal sub1out_12_OBUF_CYMUXG2 : STD_LOGIC; 
  signal sub1out_12_OBUF_CYMUXF2 : STD_LOGIC; 
  signal sub1out_12_OBUF_CY0G : STD_LOGIC; 
  signal sub1out_12_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_9_N96 : STD_LOGIC; 
  signal sub1out_12_OBUF_CLKINV : STD_LOGIC; 
  signal sub1out_14_OBUF_FFY_RST : STD_LOGIC; 
  signal sub1out_14_OBUF_DXMUX : STD_LOGIC; 
  signal sub1out_14_OBUF_XORF : STD_LOGIC; 
  signal sub1out_14_OBUF_CYINIT : STD_LOGIC; 
  signal sub1out_14_OBUF_CY0F : STD_LOGIC; 
  signal sub1out_14_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_9_N102 : STD_LOGIC; 
  signal sub1out_14_OBUF_DYMUX : STD_LOGIC; 
  signal sub1out_14_OBUF_XORG : STD_LOGIC; 
  signal XLXI_9_N105 : STD_LOGIC; 
  signal XLXI_9_N108 : STD_LOGIC; 
  signal sub1out_14_OBUF_CLKINV : STD_LOGIC; 
  signal XLXI_10_N27_CYINIT : STD_LOGIC; 
  signal XLXI_10_N27_CY0F : STD_LOGIC; 
  signal XLXI_10_N27_CYSELF : STD_LOGIC; 
  signal XLXI_10_N18 : STD_LOGIC; 
  signal XLXI_10_N27_BXINVNOT : STD_LOGIC; 
  signal XLXI_10_N27_CYMUXG : STD_LOGIC; 
  signal XLXI_10_N21 : STD_LOGIC; 
  signal XLXI_10_N27_CY0G : STD_LOGIC; 
  signal XLXI_10_N27_CYSELG : STD_LOGIC; 
  signal XLXI_10_N24 : STD_LOGIC; 
  signal XLXI_10_N39_CY0F : STD_LOGIC; 
  signal XLXI_10_N30 : STD_LOGIC; 
  signal XLXI_10_N39_CYSELF : STD_LOGIC; 
  signal XLXI_10_N39_CYMUXFAST : STD_LOGIC; 
  signal XLXI_10_N39_CYAND : STD_LOGIC; 
  signal XLXI_10_N39_FASTCARRY : STD_LOGIC; 
  signal XLXI_10_N39_CYMUXG2 : STD_LOGIC; 
  signal XLXI_10_N39_CYMUXF2 : STD_LOGIC; 
  signal XLXI_10_N39_CY0G : STD_LOGIC; 
  signal XLXI_10_N39_CYSELG : STD_LOGIC; 
  signal XLXI_10_N36 : STD_LOGIC; 
  signal XLXI_10_N51_CY0F : STD_LOGIC; 
  signal XLXI_10_N42 : STD_LOGIC; 
  signal XLXI_10_N51_CYSELF : STD_LOGIC; 
  signal XLXI_10_N51_CYMUXFAST : STD_LOGIC; 
  signal XLXI_10_N51_CYAND : STD_LOGIC; 
  signal XLXI_10_N51_FASTCARRY : STD_LOGIC; 
  signal XLXI_10_N51_CYMUXG2 : STD_LOGIC; 
  signal XLXI_10_N51_CYMUXF2 : STD_LOGIC; 
  signal XLXI_10_N51_CY0G : STD_LOGIC; 
  signal XLXI_10_N51_CYSELG : STD_LOGIC; 
  signal XLXI_10_N48 : STD_LOGIC; 
  signal XLXI_10_N63_CY0F : STD_LOGIC; 
  signal XLXI_10_N54 : STD_LOGIC; 
  signal XLXI_10_N63_CYSELF : STD_LOGIC; 
  signal XLXI_10_N63_CYMUXFAST : STD_LOGIC; 
  signal XLXI_10_N63_CYAND : STD_LOGIC; 
  signal XLXI_10_N63_FASTCARRY : STD_LOGIC; 
  signal XLXI_10_N63_CYMUXG2 : STD_LOGIC; 
  signal XLXI_10_N63_CYMUXF2 : STD_LOGIC; 
  signal XLXI_10_N63_CY0G : STD_LOGIC; 
  signal XLXI_10_N63_CYSELG : STD_LOGIC; 
  signal XLXI_10_N60 : STD_LOGIC; 
  signal XLXN_28_9_CYINIT : STD_LOGIC; 
  signal XLXN_28_9_CY0F : STD_LOGIC; 
  signal XLXI_10_N66 : STD_LOGIC; 
  signal XLXN_28_9_DYMUX : STD_LOGIC; 
  signal XLXN_28_9_XORG : STD_LOGIC; 
  signal XLXI_10_N69 : STD_LOGIC; 
  signal XLXN_28_9_CYSELF : STD_LOGIC; 
  signal XLXN_28_9_CYMUXFAST : STD_LOGIC; 
  signal XLXN_28_9_CYAND : STD_LOGIC; 
  signal XLXN_28_9_FASTCARRY : STD_LOGIC; 
  signal XLXN_28_9_CYMUXG2 : STD_LOGIC; 
  signal XLXN_28_9_CYMUXF2 : STD_LOGIC; 
  signal XLXN_28_9_CY0G : STD_LOGIC; 
  signal XLXN_28_9_CYSELG : STD_LOGIC; 
  signal XLXI_10_N72 : STD_LOGIC; 
  signal XLXN_28_9_CLKINV : STD_LOGIC; 
  signal XLXN_28_10_FFX_RST : STD_LOGIC; 
  signal XLXN_28_10_FFY_RST : STD_LOGIC; 
  signal XLXN_28_10_DXMUX : STD_LOGIC; 
  signal XLXN_28_10_XORF : STD_LOGIC; 
  signal XLXN_28_10_CYINIT : STD_LOGIC; 
  signal XLXN_28_10_CY0F : STD_LOGIC; 
  signal XLXI_10_N78 : STD_LOGIC; 
  signal XLXN_28_10_DYMUX : STD_LOGIC; 
  signal XLXN_28_10_XORG : STD_LOGIC; 
  signal XLXI_10_N81 : STD_LOGIC; 
  signal XLXN_28_10_CYSELF : STD_LOGIC; 
  signal XLXN_28_10_CYMUXFAST : STD_LOGIC; 
  signal XLXN_28_10_CYAND : STD_LOGIC; 
  signal XLXN_28_10_FASTCARRY : STD_LOGIC; 
  signal XLXN_28_10_CYMUXG2 : STD_LOGIC; 
  signal XLXN_28_10_CYMUXF2 : STD_LOGIC; 
  signal XLXN_28_10_CY0G : STD_LOGIC; 
  signal XLXN_28_10_CYSELG : STD_LOGIC; 
  signal XLXI_10_N84 : STD_LOGIC; 
  signal XLXN_28_10_CLKINV : STD_LOGIC; 
  signal XLXI_4_N212_FFX_RST : STD_LOGIC; 
  signal XLXN_28_12_DXMUX : STD_LOGIC; 
  signal XLXN_28_12_XORF : STD_LOGIC; 
  signal XLXN_28_12_CYINIT : STD_LOGIC; 
  signal XLXN_28_12_CY0F : STD_LOGIC; 
  signal XLXI_10_N90 : STD_LOGIC; 
  signal XLXN_28_12_DYMUX : STD_LOGIC; 
  signal XLXN_28_12_XORG : STD_LOGIC; 
  signal XLXI_10_N93 : STD_LOGIC; 
  signal XLXN_28_12_CYSELF : STD_LOGIC; 
  signal XLXN_28_12_CYMUXFAST : STD_LOGIC; 
  signal XLXN_28_12_CYAND : STD_LOGIC; 
  signal XLXN_28_12_FASTCARRY : STD_LOGIC; 
  signal XLXN_28_12_CYMUXG2 : STD_LOGIC; 
  signal XLXN_28_12_CYMUXF2 : STD_LOGIC; 
  signal XLXN_28_12_CY0G : STD_LOGIC; 
  signal XLXN_28_12_CYSELG : STD_LOGIC; 
  signal XLXI_10_N96 : STD_LOGIC; 
  signal XLXN_28_12_CLKINV : STD_LOGIC; 
  signal XLXN_28_14_DXMUX : STD_LOGIC; 
  signal XLXN_28_14_XORF : STD_LOGIC; 
  signal XLXN_28_14_CYINIT : STD_LOGIC; 
  signal XLXN_28_14_CY0F : STD_LOGIC; 
  signal XLXN_28_14_CYSELF : STD_LOGIC; 
  signal XLXI_10_N102 : STD_LOGIC; 
  signal XLXN_28_14_DYMUX : STD_LOGIC; 
  signal XLXN_28_14_XORG : STD_LOGIC; 
  signal XLXI_10_N105 : STD_LOGIC; 
  signal XLXI_10_N108 : STD_LOGIC; 
  signal XLXN_28_14_CLKINV : STD_LOGIC; 
  signal xkr1_0_OBUF_DXMUX : STD_LOGIC; 
  signal xkr1_0_OBUF_XORF : STD_LOGIC; 
  signal xkr1_0_OBUF_CYINIT : STD_LOGIC; 
  signal xkr1_0_OBUF_CY0F : STD_LOGIC; 
  signal xkr1_0_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_11_N10 : STD_LOGIC; 
  signal xkr1_0_OBUF_BXINVNOT : STD_LOGIC; 
  signal xkr1_0_OBUF_DYMUX : STD_LOGIC; 
  signal xkr1_0_OBUF_XORG : STD_LOGIC; 
  signal xkr1_0_OBUF_CYMUXG : STD_LOGIC; 
  signal XLXI_11_N13 : STD_LOGIC; 
  signal xkr1_0_OBUF_CY0G : STD_LOGIC; 
  signal xkr1_0_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_11_N16 : STD_LOGIC; 
  signal xkr1_0_OBUF_CLKINV : STD_LOGIC; 
  signal xkr1_2_OBUF_FFX_RST : STD_LOGIC; 
  signal xkr1_2_OBUF_DXMUX : STD_LOGIC; 
  signal xkr1_2_OBUF_XORF : STD_LOGIC; 
  signal xkr1_2_OBUF_CYINIT : STD_LOGIC; 
  signal xkr1_2_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_11_N22 : STD_LOGIC; 
  signal xkr1_2_OBUF_DYMUX : STD_LOGIC; 
  signal xkr1_2_OBUF_XORG : STD_LOGIC; 
  signal XLXI_11_N25 : STD_LOGIC; 
  signal xkr1_2_OBUF_CYSELF : STD_LOGIC; 
  signal xkr1_2_OBUF_CYMUXFAST : STD_LOGIC; 
  signal xkr1_2_OBUF_CYAND : STD_LOGIC; 
  signal xkr1_2_OBUF_FASTCARRY : STD_LOGIC; 
  signal xkr1_2_OBUF_CYMUXG2 : STD_LOGIC; 
  signal xkr1_2_OBUF_CYMUXF2 : STD_LOGIC; 
  signal xkr1_2_OBUF_CY0G : STD_LOGIC; 
  signal xkr1_2_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_11_N28 : STD_LOGIC; 
  signal xkr1_2_OBUF_CLKINV : STD_LOGIC; 
  signal xkr1_4_OBUF_FFY_RST : STD_LOGIC; 
  signal xkr1_4_OBUF_FFX_RST : STD_LOGIC; 
  signal xkr1_4_OBUF_DXMUX : STD_LOGIC; 
  signal xkr1_4_OBUF_XORF : STD_LOGIC; 
  signal xkr1_4_OBUF_CYINIT : STD_LOGIC; 
  signal xkr1_4_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_11_N34 : STD_LOGIC; 
  signal xkr1_4_OBUF_DYMUX : STD_LOGIC; 
  signal xkr1_4_OBUF_XORG : STD_LOGIC; 
  signal XLXI_11_N37 : STD_LOGIC; 
  signal xkr1_4_OBUF_CYSELF : STD_LOGIC; 
  signal xkr1_4_OBUF_CYMUXFAST : STD_LOGIC; 
  signal xkr1_4_OBUF_CYAND : STD_LOGIC; 
  signal xkr1_4_OBUF_FASTCARRY : STD_LOGIC; 
  signal xkr1_4_OBUF_CYMUXG2 : STD_LOGIC; 
  signal xkr1_4_OBUF_CYMUXF2 : STD_LOGIC; 
  signal xkr1_4_OBUF_CY0G : STD_LOGIC; 
  signal xkr1_4_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_11_N40 : STD_LOGIC; 
  signal xkr1_4_OBUF_CLKINV : STD_LOGIC; 
  signal xkr1_6_OBUF_FFX_RST : STD_LOGIC; 
  signal xkr1_6_OBUF_FFY_RST : STD_LOGIC; 
  signal xkr1_6_OBUF_DXMUX : STD_LOGIC; 
  signal xkr1_6_OBUF_XORF : STD_LOGIC; 
  signal xkr1_6_OBUF_CYINIT : STD_LOGIC; 
  signal xkr1_6_OBUF_CY0F : STD_LOGIC; 
  signal xkr1_6_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_11_N46 : STD_LOGIC; 
  signal xkr1_6_OBUF_DYMUX : STD_LOGIC; 
  signal xkr1_6_OBUF_XORG : STD_LOGIC; 
  signal XLXI_11_N49 : STD_LOGIC; 
  signal XLXI_11_N52 : STD_LOGIC; 
  signal xkr1_6_OBUF_CLKINV : STD_LOGIC; 
  signal xki1_0_OBUF_FFY_RST : STD_LOGIC; 
  signal xki1_0_OBUF_DXMUX : STD_LOGIC; 
  signal xki1_0_OBUF_XORF : STD_LOGIC; 
  signal xki1_0_OBUF_CYINIT : STD_LOGIC; 
  signal xki1_0_OBUF_CY0F : STD_LOGIC; 
  signal xki1_0_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_12_N10 : STD_LOGIC; 
  signal xki1_0_OBUF_BXINVNOT : STD_LOGIC; 
  signal xki1_0_OBUF_DYMUX : STD_LOGIC; 
  signal xki1_0_OBUF_XORG : STD_LOGIC; 
  signal xki1_0_OBUF_CYMUXG : STD_LOGIC; 
  signal XLXI_12_N13 : STD_LOGIC; 
  signal xki1_0_OBUF_CY0G : STD_LOGIC; 
  signal xki1_0_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_12_N16 : STD_LOGIC; 
  signal xki1_0_OBUF_CLKINV : STD_LOGIC; 
  signal xki1_2_OBUF_DXMUX : STD_LOGIC; 
  signal xki1_2_OBUF_XORF : STD_LOGIC; 
  signal xki1_2_OBUF_CYINIT : STD_LOGIC; 
  signal xki1_2_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_12_N22 : STD_LOGIC; 
  signal xki1_2_OBUF_DYMUX : STD_LOGIC; 
  signal xki1_2_OBUF_XORG : STD_LOGIC; 
  signal XLXI_12_N25 : STD_LOGIC; 
  signal xki1_2_OBUF_CYSELF : STD_LOGIC; 
  signal xki1_2_OBUF_CYMUXFAST : STD_LOGIC; 
  signal xki1_2_OBUF_CYAND : STD_LOGIC; 
  signal xki1_2_OBUF_FASTCARRY : STD_LOGIC; 
  signal xki1_2_OBUF_CYMUXG2 : STD_LOGIC; 
  signal xki1_2_OBUF_CYMUXF2 : STD_LOGIC; 
  signal xki1_2_OBUF_CY0G : STD_LOGIC; 
  signal xki1_2_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_12_N28 : STD_LOGIC; 
  signal xki1_2_OBUF_CLKINV : STD_LOGIC; 
  signal xki1_4_OBUF_DXMUX : STD_LOGIC; 
  signal xki1_4_OBUF_XORF : STD_LOGIC; 
  signal xki1_4_OBUF_CYINIT : STD_LOGIC; 
  signal xki1_4_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_12_N34 : STD_LOGIC; 
  signal xki1_4_OBUF_DYMUX : STD_LOGIC; 
  signal xki1_4_OBUF_XORG : STD_LOGIC; 
  signal XLXI_12_N37 : STD_LOGIC; 
  signal xki1_4_OBUF_CYSELF : STD_LOGIC; 
  signal xki1_4_OBUF_CYMUXFAST : STD_LOGIC; 
  signal xki1_4_OBUF_CYAND : STD_LOGIC; 
  signal xki1_4_OBUF_FASTCARRY : STD_LOGIC; 
  signal xki1_4_OBUF_CYMUXG2 : STD_LOGIC; 
  signal xki1_4_OBUF_CYMUXF2 : STD_LOGIC; 
  signal xki1_4_OBUF_CY0G : STD_LOGIC; 
  signal xki1_4_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_12_N40 : STD_LOGIC; 
  signal xki1_4_OBUF_CLKINV : STD_LOGIC; 
  signal XLXI_4_N210_FFY_RST : STD_LOGIC; 
  signal xki1_6_OBUF_DXMUX : STD_LOGIC; 
  signal xki1_6_OBUF_XORF : STD_LOGIC; 
  signal xki1_6_OBUF_CYINIT : STD_LOGIC; 
  signal xki1_6_OBUF_CY0F : STD_LOGIC; 
  signal xki1_6_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_12_N46 : STD_LOGIC; 
  signal xki1_6_OBUF_DYMUX : STD_LOGIC; 
  signal xki1_6_OBUF_XORG : STD_LOGIC; 
  signal XLXI_12_N49 : STD_LOGIC; 
  signal XLXI_12_N52 : STD_LOGIC; 
  signal xki1_6_OBUF_CLKINV : STD_LOGIC; 
  signal xkr2_0_OBUF_DXMUX : STD_LOGIC; 
  signal xkr2_0_OBUF_XORF : STD_LOGIC; 
  signal xkr2_0_OBUF_CYINIT : STD_LOGIC; 
  signal xkr2_0_OBUF_CY0F : STD_LOGIC; 
  signal xkr2_0_OBUF_CYSELF : STD_LOGIC; 
  signal XLXI_13_N10 : STD_LOGIC; 
  signal xkr2_0_OBUF_DYMUX : STD_LOGIC; 
  signal xkr2_0_OBUF_XORG : STD_LOGIC; 
  signal xkr2_0_OBUF_CYMUXG : STD_LOGIC; 
  signal XLXI_13_N13 : STD_LOGIC; 
  signal xkr2_0_OBUF_CY0G : STD_LOGIC; 
  signal xkr2_0_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_13_N16 : STD_LOGIC; 
  signal xkr2_0_OBUF_CLKINV : STD_LOGIC; 
  signal xkr2_2_OBUF_DXMUX : STD_LOGIC; 
  signal xkr2_2_OBUF_XORF : STD_LOGIC; 
  signal xkr2_2_OBUF_CYINIT : STD_LOGIC; 
  signal xkr2_2_OBUF_CY0F : STD_LOGIC; 
  signal XLXI_13_N22 : STD_LOGIC; 
  signal xkr2_2_OBUF_DYMUX : STD_LOGIC; 
  signal xkr2_2_OBUF_XORG : STD_LOGIC; 
  signal XLXI_13_N25 : STD_LOGIC; 
  signal xkr2_2_OBUF_CYSELF : STD_LOGIC; 
  signal xkr2_2_OBUF_CYMUXFAST : STD_LOGIC; 
  signal xkr2_2_OBUF_CYAND : STD_LOGIC; 
  signal xkr2_2_OBUF_FASTCARRY : STD_LOGIC; 
  signal xkr2_2_OBUF_CYMUXG2 : STD_LOGIC; 
  signal xkr2_2_OBUF_CYMUXF2 : STD_LOGIC; 
  signal xkr2_2_OBUF_CY0G : STD_LOGIC; 
  signal xkr2_2_OBUF_CYSELG : STD_LOGIC; 
  signal XLXI_13_N28 : STD_LOGIC; 
  signal xkr2_2_OBUF_CLKINV : STD_LOGIC; 
  signal xkr2_4_OBUF_DXMUX : STD_LOGIC; 
  signal xkr2_4_OBUF_XORF : STD_LOGIC; 
  signal xkr2_4_OBUF_CYINIT : STD_LOGIC; 
  signal xkr2_4_OBUF_CY0F : STD_LOGIC;