top_sh3_timesim.vhd

FPGA开发光盘各章节实例的设计工程与源码

-- Xilinx Vhdl netlist produced by netgen application (version G.26)
-- Command       : -intstyle ise -s 6 -pcf top_sh3.pcf -ngm top_sh3.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim top_sh3.ncd top_sh3_timesim.vhd 
-- Input file    : top_sh3.ncd
-- Output file   : top_sh3_timesim.vhd
-- Design name   : top_sh3
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2v3000bf957-6 (PRODUCTION 1.116 2003-11-04, STEPPING 0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity top_sh3 is
  port (
    clock : in STD_LOGIC := 'X'; 
    contr2out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xki2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xki1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    mulout2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    mulout1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    sub1out : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    indiv2out : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xkr2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xkr1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xr2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xr1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    wr : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    wi : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xi2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xi1 : in STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end top_sh3;

architecture Structure of top_sh3 is
  signal XLXI_4_N193 : STD_LOGIC; 
  signal XLXI_4_N192 : STD_LOGIC; 
  signal clock_BUFGP : STD_LOGIC; 
  signal XLXI_4_N190 : STD_LOGIC; 
  signal XLXI_4_N191 : STD_LOGIC; 
  signal XLXI_4_N201 : STD_LOGIC; 
  signal XLXI_4_N200 : STD_LOGIC; 
  signal XLXI_4_N198 : STD_LOGIC; 
  signal XLXI_4_N199 : STD_LOGIC; 
  signal XLXI_4_N196 : STD_LOGIC; 
  signal XLXI_4_N197 : STD_LOGIC; 
  signal XLXI_4_N194 : STD_LOGIC; 
  signal XLXI_4_N195 : STD_LOGIC; 
  signal XLXI_4_N188 : STD_LOGIC; 
  signal XLXI_4_N189 : STD_LOGIC; 
  signal XLXI_4_N186 : STD_LOGIC; 
  signal XLXI_4_N187 : STD_LOGIC; 
  signal wr_7_IBUF : STD_LOGIC; 
  signal xi2_7_IBUF : STD_LOGIC; 
  signal XLXI_4_N209 : STD_LOGIC; 
  signal XLXI_4_N208 : STD_LOGIC; 
  signal XLXI_4_N206 : STD_LOGIC; 
  signal XLXI_4_N207 : STD_LOGIC; 
  signal XLXI_4_N217 : STD_LOGIC; 
  signal XLXI_4_N216 : STD_LOGIC; 
  signal XLXI_4_N214 : STD_LOGIC; 
  signal XLXI_4_N215 : STD_LOGIC; 
  signal XLXI_4_N212 : STD_LOGIC; 
  signal XLXI_4_N213 : STD_LOGIC; 
  signal XLXI_4_N210 : STD_LOGIC; 
  signal XLXI_4_N211 : STD_LOGIC; 
  signal XLXI_4_N204 : STD_LOGIC; 
  signal XLXI_4_N205 : STD_LOGIC; 
  signal XLXI_4_N202 : STD_LOGIC; 
  signal XLXI_4_N203 : STD_LOGIC; 
  signal wr_0_IBUF : STD_LOGIC; 
  signal wr_1_IBUF : STD_LOGIC; 
  signal wr_2_IBUF : STD_LOGIC; 
  signal wr_3_IBUF : STD_LOGIC; 
  signal wr_4_IBUF : STD_LOGIC; 
  signal wr_5_IBUF : STD_LOGIC; 
  signal wr_6_IBUF : STD_LOGIC; 
  signal xi2_0_IBUF : STD_LOGIC; 
  signal xi2_1_IBUF : STD_LOGIC; 
  signal xi2_2_IBUF : STD_LOGIC; 
  signal xi2_3_IBUF : STD_LOGIC; 
  signal xi2_4_IBUF : STD_LOGIC; 
  signal xi2_5_IBUF : STD_LOGIC; 
  signal xi2_6_IBUF : STD_LOGIC; 
  signal XLXI_3_N193 : STD_LOGIC; 
  signal XLXI_3_N192 : STD_LOGIC; 
  signal XLXI_3_N190 : STD_LOGIC; 
  signal XLXI_3_N191 : STD_LOGIC; 
  signal XLXI_3_N201 : STD_LOGIC; 
  signal XLXI_3_N200 : STD_LOGIC; 
  signal XLXI_3_N198 : STD_LOGIC; 
  signal XLXI_3_N199 : STD_LOGIC; 
  signal XLXI_3_N196 : STD_LOGIC; 
  signal XLXI_3_N197 : STD_LOGIC; 
  signal XLXI_3_N194 : STD_LOGIC; 
  signal XLXI_3_N195 : STD_LOGIC; 
  signal XLXI_3_N188 : STD_LOGIC; 
  signal XLXI_3_N189 : STD_LOGIC; 
  signal XLXI_3_N186 : STD_LOGIC; 
  signal XLXI_3_N187 : STD_LOGIC; 
  signal wi_7_IBUF : STD_LOGIC; 
  signal xr2_7_IBUF : STD_LOGIC; 
  signal XLXI_3_N209 : STD_LOGIC; 
  signal XLXI_3_N208 : STD_LOGIC; 
  signal XLXI_3_N206 : STD_LOGIC; 
  signal XLXI_3_N207 : STD_LOGIC; 
  signal XLXI_3_N217 : STD_LOGIC; 
  signal XLXI_3_N216 : STD_LOGIC; 
  signal XLXI_3_N214 : STD_LOGIC; 
  signal XLXI_3_N215 : STD_LOGIC; 
  signal XLXI_3_N212 : STD_LOGIC; 
  signal XLXI_3_N213 : STD_LOGIC; 
  signal XLXI_3_N210 : STD_LOGIC; 
  signal XLXI_3_N211 : STD_LOGIC; 
  signal XLXI_3_N204 : STD_LOGIC; 
  signal XLXI_3_N205 : STD_LOGIC; 
  signal XLXI_3_N202 : STD_LOGIC; 
  signal XLXI_3_N203 : STD_LOGIC; 
  signal wi_0_IBUF : STD_LOGIC; 
  signal wi_1_IBUF : STD_LOGIC; 
  signal wi_2_IBUF : STD_LOGIC; 
  signal wi_3_IBUF : STD_LOGIC; 
  signal wi_4_IBUF : STD_LOGIC; 
  signal wi_5_IBUF : STD_LOGIC; 
  signal wi_6_IBUF : STD_LOGIC; 
  signal xr2_0_IBUF : STD_LOGIC; 
  signal xr2_1_IBUF : STD_LOGIC; 
  signal xr2_2_IBUF : STD_LOGIC; 
  signal xr2_3_IBUF : STD_LOGIC; 
  signal xr2_4_IBUF : STD_LOGIC; 
  signal xr2_5_IBUF : STD_LOGIC; 
  signal xr2_6_IBUF : STD_LOGIC; 
  signal XLXI_2_N193 : STD_LOGIC; 
  signal XLXI_2_N192 : STD_LOGIC; 
  signal XLXI_2_N190 : STD_LOGIC; 
  signal XLXI_2_N191 : STD_LOGIC; 
  signal XLXI_2_N201 : STD_LOGIC; 
  signal XLXI_2_N200 : STD_LOGIC; 
  signal XLXI_2_N198 : STD_LOGIC; 
  signal XLXI_2_N199 : STD_LOGIC; 
  signal XLXI_2_N196 : STD_LOGIC; 
  signal XLXI_2_N197 : STD_LOGIC; 
  signal XLXI_2_N194 : STD_LOGIC; 
  signal XLXI_2_N195 : STD_LOGIC; 
  signal XLXI_2_N188 : STD_LOGIC; 
  signal XLXI_2_N189 : STD_LOGIC; 
  signal XLXI_2_N186 : STD_LOGIC; 
  signal XLXI_2_N187 : STD_LOGIC; 
  signal XLXI_2_N209 : STD_LOGIC; 
  signal XLXI_2_N208 : STD_LOGIC; 
  signal XLXI_2_N206 : STD_LOGIC; 
  signal XLXI_2_N207 : STD_LOGIC; 
  signal XLXI_2_N217 : STD_LOGIC; 
  signal XLXI_2_N216 : STD_LOGIC; 
  signal XLXI_2_N214 : STD_LOGIC; 
  signal XLXI_2_N215 : STD_LOGIC; 
  signal XLXI_2_N212 : STD_LOGIC; 
  signal XLXI_2_N213 : STD_LOGIC; 
  signal XLXI_2_N210 : STD_LOGIC; 
  signal XLXI_2_N211 : STD_LOGIC; 
  signal XLXI_2_N204 : STD_LOGIC; 
  signal XLXI_2_N205 : STD_LOGIC; 
  signal XLXI_2_N202 : STD_LOGIC; 
  signal XLXI_2_N203 : STD_LOGIC; 
  signal XLXI_1_N193 : STD_LOGIC; 
  signal XLXI_1_N192 : STD_LOGIC; 
  signal XLXI_1_N190 : STD_LOGIC; 
  signal XLXI_1_N191 : STD_LOGIC; 
  signal XLXI_1_N201 : STD_LOGIC; 
  signal XLXI_1_N200 : STD_LOGIC; 
  signal XLXI_1_N198 : STD_LOGIC; 
  signal XLXI_1_N199 : STD_LOGIC; 
  signal XLXI_1_N196 : STD_LOGIC; 
  signal XLXI_1_N197 : STD_LOGIC; 
  signal XLXI_1_N194 : STD_LOGIC; 
  signal XLXI_1_N195 : STD_LOGIC; 
  signal XLXI_1_N188 : STD_LOGIC; 
  signal XLXI_1_N189 : STD_LOGIC; 
  signal XLXI_1_N186 : STD_LOGIC; 
  signal XLXI_1_N187 : STD_LOGIC; 
  signal XLXI_1_N209 : STD_LOGIC; 
  signal XLXI_1_N208 : STD_LOGIC; 
  signal XLXI_1_N206 : STD_LOGIC; 
  signal XLXI_1_N207 : STD_LOGIC; 
  signal XLXI_1_N217 : STD_LOGIC; 
  signal XLXI_1_N216 : STD_LOGIC; 
  signal XLXI_1_N214 : STD_LOGIC; 
  signal XLXI_1_N215 : STD_LOGIC; 
  signal XLXI_1_N212 : STD_LOGIC; 
  signal XLXI_1_N213 : STD_LOGIC; 
  signal XLXI_1_N210 : STD_LOGIC; 
  signal XLXI_1_N211 : STD_LOGIC; 
  signal XLXI_1_N204 : STD_LOGIC; 
  signal XLXI_1_N205 : STD_LOGIC; 
  signal XLXI_1_N202 : STD_LOGIC; 
  signal XLXI_1_N203 : STD_LOGIC; 
  signal XLXI_9_N2 : STD_LOGIC; 
  signal XLXI_9_N3 : STD_LOGIC; 
  signal XLXI_9_N27 : STD_LOGIC; 
  signal XLXI_9_N4 : STD_LOGIC; 
  signal XLXI_9_N5 : STD_LOGIC; 
  signal XLXI_9_N39 : STD_LOGIC; 
  signal XLXI_9_N6 : STD_LOGIC; 
  signal XLXI_9_N7 : STD_LOGIC; 
  signal XLXI_9_N51 : STD_LOGIC; 
  signal XLXI_9_N8 : STD_LOGIC; 
  signal XLXI_9_N9 : STD_LOGIC; 
  signal XLXI_9_N63 : STD_LOGIC; 
  signal XLXI_9_N10 : STD_LOGIC; 
  signal XLXI_9_N11 : STD_LOGIC; 
  signal XLXI_9_N75 : STD_LOGIC; 
  signal XLXI_9_N12 : STD_LOGIC; 
  signal XLXI_9_N13 : STD_LOGIC; 
  signal XLXI_9_N87 : STD_LOGIC; 
  signal XLXI_9_N14 : STD_LOGIC; 
  signal XLXI_9_N15 : STD_LOGIC; 
  signal XLXI_9_N99 : STD_LOGIC; 
  signal XLXI_9_N16 : STD_LOGIC; 
  signal XLXI_9_N17 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal sub1out_0_OBUF : STD_LOGIC; 
  signal sub1out_1_OBUF : STD_LOGIC; 
  signal sub1out_2_OBUF : STD_LOGIC; 
  signal sub1out_3_OBUF : STD_LOGIC; 
  signal sub1out_4_OBUF : STD_LOGIC; 
  signal sub1out_5_OBUF : STD_LOGIC; 
  signal sub1out_6_OBUF : STD_LOGIC; 
  signal sub1out_7_OBUF : STD_LOGIC; 
  signal sub1out_8_OBUF : STD_LOGIC; 
  signal sub1out_9_OBUF : STD_LOGIC; 
  signal sub1out_10_OBUF : STD_LOGIC; 
  signal sub1out_11_OBUF : STD_LOGIC; 
  signal sub1out_12_OBUF : STD_LOGIC; 
  signal sub1out_13_OBUF : STD_LOGIC; 
  signal sub1out_14_OBUF : STD_LOGIC; 
  signal sub1out_15_OBUF : STD_LOGIC; 
  signal XLXI_10_N27 : STD_LOGIC; 
  signal XLXI_10_N39 : STD_LOGIC; 
  signal XLXI_10_N51 : STD_LOGIC; 
  signal XLXI_10_N63 : STD_LOGIC; 
  signal XLXI_10_N11 : STD_LOGIC; 
  signal XLXI_10_N75 : STD_LOGIC; 
  signal XLXI_10_N12 : STD_LOGIC; 
  signal XLXI_10_N13 : STD_LOGIC; 
  signal XLXI_10_N87 : STD_LOGIC; 
  signal XLXI_10_N14 : STD_LOGIC; 
  signal XLXI_10_N15 : STD_LOGIC; 
  signal XLXI_10_N99 : STD_LOGIC; 
  signal XLXI_10_N16 : STD_LOGIC; 
  signal XLXI_10_N17 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal XLXI_11_N2 : STD_LOGIC; 
  signal XLXI_11_N3 : STD_LOGIC; 
  signal XLXI_11_N19 : STD_LOGIC; 
  signal XLXI_11_N4 : STD_LOGIC; 
  signal XLXI_11_N5 : STD_LOGIC; 
  signal XLXI_11_N31 : STD_LOGIC; 
  signal XLXI_11_N6 : STD_LOGIC; 
  signal XLXI_11_N7 : STD_LOGIC; 
  signal XLXI_11_N43 : STD_LOGIC; 
  signal XLXI_19_outdat_x_7_Q : STD_LOGIC; 
  signal XLXI_21_outdat_temp_7_Q : STD_LOGIC; 
  signal XLXI_11_N8 : STD_LOGIC; 
  signal XLXI_11_N9 : STD_LOGIC; 
  signal XLXI_19_outdat_x_0_Q : STD_LOGIC; 
  signal XLXI_21_outdat_temp_0_Q : STD_LOGIC; 
  signal XLXI_19_outdat_x_1_Q : STD_LOGIC; 
  signal XLXI_21_outdat_temp_1_Q : STD_LOGIC; 
  signal xkr1_0_OBUF : STD_LOGIC; 
  signal xkr1_1_OBUF : STD_LOGIC; 
  signal XLXI_19_outdat_x_2_Q : STD_LOGIC; 
  signal XLXI_21_outdat_temp_2_Q : STD_LOGIC; 
  signal XLXI_19_outdat_x_3_Q : STD_LOGIC; 
  signal XLXI_21_outdat_temp_3_Q : STD_LOGIC; 
  signal xkr1_2_OBUF : STD_LOGIC; 
  signal xkr1_3_OBUF : STD_LOGIC; 
  signal XLXI_19_outdat_x_4_Q : STD_LOGIC; 
  signal XLXI_21_outdat_temp_4_Q : STD_LOGIC; 
  signal XLXI_19_outdat_x_5_Q : STD_LOGIC; 
  signal XLXI_21_outdat_temp_5_Q : STD_LOGIC; 
  signal xkr1_4_OBUF : STD_LOGIC; 
  signal xkr1_5_OBUF : STD_LOGIC; 
  signal xkr1_6_OBUF : STD_LOGIC; 
  signal xkr1_7_OBUF : STD_LOGIC; 
  signal XLXI_12_N2 : STD_LOGIC; 
  signal XLXI_12_N3 : STD_LOGIC; 
  signal XLXI_12_N19 : STD_LOGIC; 
  signal XLXI_12_N4 : STD_LOGIC; 
  signal XLXI_12_N5 : STD_LOGIC; 
  signal XLXI_12_N31 : STD_LOGIC; 
  signal XLXI_12_N6 : STD_LOGIC; 
  signal XLXI_12_N7 : STD_LOGIC; 
  signal XLXI_12_N43 : STD_LOGIC; 
  signal XLXI_20_outdat_x_7_Q : STD_LOGIC; 
  signal XLXI_22_outdat_temp_7_Q : STD_LOGIC; 
  signal XLXI_12_N8 : STD_LOGIC; 
  signal XLXI_12_N9 : STD_LOGIC; 
  signal XLXI_20_outdat_x_0_Q : STD_LOGIC; 
  signal XLXI_22_outdat_temp_0_Q : STD_LOGIC; 
  signal XLXI_20_outdat_x_1_Q : STD_LOGIC; 
  signal XLXI_22_outdat_temp_1_Q : STD_LOGIC; 
  signal xki1_0_OBUF : STD_LOGIC; 
  signal xki1_1_OBUF : STD_LOGIC; 
  signal XLXI_20_outdat_x_2_Q : STD_LOGIC; 
  signal XLXI_22_outdat_temp_2_Q : STD_LOGIC; 
  signal XLXI_20_outdat_x_3_Q : STD_LOGIC; 
  signal XLXI_22_outdat_temp_3_Q : STD_LOGIC; 
  signal xki1_2_OBUF : STD_LOGIC; 
  signal xki1_3_OBUF : STD_LOGIC; 
  signal XLXI_20_outdat_x_4_Q : STD_LOGIC; 
  signal XLXI_22_outdat_temp_4_Q : STD_LOGIC; 
  signal XLXI_20_outdat_x_5_Q : STD_LOGIC; 
  signal XLXI_22_outdat_temp_5_Q : STD_LOGIC; 
  signal xki1_4_OBUF : STD_LOGIC; 
  signal xki1_5_OBUF : STD_LOGIC; 
  signal xki1_6_OBUF : STD_LOGIC; 
  signal xki1_7_OBUF : STD_LOGIC; 
  signal XLXI_13_N2 : STD_LOGIC; 
  signal XLXI_13_N3 : STD_LOGIC;