core_sub16clk.xco

FPGA开发光盘各章节实例的设计工程与源码

# Xilinx CORE Generator 6.1.03i
# Username = administrator
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = E:\51sh\sh3
# ExpandedProjectPath = E:\51sh\sh3
# OverwriteFiles = true
# Core name: core_sub16clk
# Number of Primitives in design: 63
# Number of CLBs used in design: 4
# Number of Slices used in design: 8
# Number of LUT sites used in design: 16
# Number of LUTs used in design: 16
# Number of REG used in design: 16
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 1
# Huset "default" = (0, 0) to (1, 4) in CLBs
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET SimulationOutputProducts = VHDL
SET XilinxFamily = Virtex2
SET OutputOption = DesignFlow
SET DesignFlow = VHDL
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SELECT Adder_Subtracter Virtex2 Xilinx,_Inc. 6.0
CSET async_init_value = 0
CSET create_rpm = true
CSET clock_enable = false
CSET output_options = registered
CSET overflow_output = false
CSET port_b_constant = false
CSET port_b_width = 16
CSET port_a_width = 16
CSET ce_overrides = sync_controls_override_ce
CSET bypass_sense = active_high
CSET port_a_sign = signed
CSET ce_override_for_bypass = true
CSET sync_init_value = 0
CSET operation = subtract
CSET latency = 1
CSET port_b_sign = signed
CSET component_name = core_sub16clk
CSET asynchronous_settings = none
CSET bypass = false
CSET carry_borrow_input = false
CSET carry_borrow_output = false
CSET port_b_constant_value = 0
CSET set_clear_priority = clear_overrides_set
CSET output_width = 16
CSET synchronous_settings = none
GENERATE