core_mul8clk.xco

FPGA开发光盘各章节实例的设计工程与源码

# Xilinx CORE Generator 6.1.03i
# Username = administrator
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = E:\51sh\sh3
# ExpandedProjectPath = E:\51sh\sh3
# OverwriteFiles = true
# Core name: core_mul8clk
# Number of Primitives in design: 49
# Number of CLBs used in design: 8
# Number of Slices used in design: 16
# Number of LUT sites used in design: 0
# Number of LUTs used in design: 0
# Number of REG used in design: 32
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 0
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 1
# Huset "core_mul8clk/top_level/par_mul_fast/m2/top" = (0, 0) to (2, 4) in CLBs
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET SimulationOutputProducts = VHDL
SET XilinxFamily = Virtex2
SET OutputOption = DesignFlow
SET DesignFlow = VHDL
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SELECT Multiplier Virtex2 Xilinx,_Inc. 6.0
CSET create_rpm = true
CSET clock_enable = false
CSET output_options = Registered
CSET port_b_constant = false
CSET port_a_input = Parallel
CSET reloadable = false
CSET port_b_width = 8
CSET nd = false
CSET multiplier_type = Parallel
CSET port_a_width = 8
CSET reload_options = Stop_During_Reload
CSET ce_overrides = CE_Overrides_SCLR
CSET memory_type = Distributed_Memory
CSET multiplier_construction = Use_Multiplier_Blocks_Virtex2
CSET port_a_data = Signed
CSET virtex2_multiplier_optimization = Speed
CSET rdy = false
CSET register_input = false
CSET port_b_data = Signed
CSET component_name = core_mul8clk
CSET synchronous_clear = false
CSET asynchronous_clear = false
CSET load_done_output = false
CSET rfd = false
CSET clk_cycles_per_input = 1
CSET style = Rectangular_Shape
CSET port_b_constant_value = 63
CSET pipelined = Minimum
CSET output_hold_register = false
CSET output_width = 16
GENERATE