absthet_core.vhd

FPGA开发光盘各章节实例的设计工程与源码

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-- You must compile the wrapper file absthet_core.vhd when simulating
-- the core, absthet_core. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY absthet_core IS
	port (
	x_in: IN std_logic_VECTOR(7 downto 0);
	y_in: IN std_logic_VECTOR(7 downto 0);
	x_out: OUT std_logic_VECTOR(7 downto 0);
	phase_out: OUT std_logic_VECTOR(7 downto 0);
	clk: IN std_logic);
END absthet_core;

ARCHITECTURE absthet_core_a OF absthet_core IS

component wrapped_absthet_core
	port (
	x_in: IN std_logic_VECTOR(7 downto 0);
	y_in: IN std_logic_VECTOR(7 downto 0);
	x_out: OUT std_logic_VECTOR(7 downto 0);
	phase_out: OUT std_logic_VECTOR(7 downto 0);
	clk: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_absthet_core use entity XilinxCoreLib.cordic_v2_0(behavioral)
		generic map(
			c_has_clk => 1,
			c_has_x_out => 1,
			c_has_y_in => 1,
			c_reg_inputs => 1,
			c_architecture => 2,
			c_input_width => 8,
			c_iterations => 0,
			c_has_rdy => 0,
			c_precision => 0,
			c_has_sclr => 0,
			c_has_nd => 0,
			c_scale_comp => 0,
			c_enable_rlocs => 1,
			c_has_phase_in => 0,
			c_has_rfd => 0,
			c_cordic_function => 1,
			c_has_ce => 0,
			c_mif_file_prefix => "cor1",
			c_round_mode => 3,
			c_has_aclr => 0,
			c_sync_enable => 1,
			c_has_y_out => 0,
			c_data_format => 0,
			c_reg_outputs => 1,
			c_coarse_rotate => 1,
			c_phase_format => 0,
			c_has_phase_out => 1,
			c_has_x_in => 1,
			c_pipeline_mode => -2,
			c_output_width => 8);
BEGIN

U0 : wrapped_absthet_core
		port map (
			x_in => x_in,
			y_in => y_in,
			x_out => x_out,
			phase_out => phase_out,
			clk => clk);
END absthet_core_a;

-- synopsys translate_on