indat_div2.vhd

FPGA开发光盘各章节实例的设计工程与源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity indat_div2 is
  port(
  			clk			: in  std_logic;
			indat_xri   : in  std_logic_vector(7 downto 0);
		   outdat_x    : out std_logic_vector(7 downto 0)	
		);
end indat_div2;

architecture rtl of indat_div2 is
	signal indat1clk,indat2clk : std_logic_vector(7 downto 0);
begin
  process(clk,indat_xri)
   begin
	  if (clk'event and clk='1')then
	  	  indat1clk<=indat_xri;
		  indat2clk<=indat1clk;
	     outdat_x<=indat2clk(7)&indat2clk(7 downto 1);		
     end if;
   end process;
end rtl;