📄 rader_hilbert.csf.rpt
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| Configuration scheme | Passive Serial |
| Hexadecimal Output File count direction | Up |
| Hexadecimal Output File start address | 0 |
| Reserve all unused pins | As output driving ground |
| Configuration device | EPC2 |
| Base pin-out file on sameframe device | Off |
| Auto user code | Off |
| Configuration device auto user code | Off |
| JTAG user code for target device | 0XFFFFFFFF |
| JTAG user code for configuration device | 0XFFFFFFFF |
+------------------------------------------------------------------+--------------------------+
+-----------------------------------------------------------------------------+
| Equations |
+-----------------------------------------------------------------------------+
The equations can be found in E:\HILBERT\rader_hilbert3\quartus\rader_hilbert.eqn.htm.
+-----------------------------------------------------------------------------+
| Floorplan View |
+-----------------------------------------------------------------------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.
+-----------------------------------------------------------------------------+
| Pin-Out File |
+-----------------------------------------------------------------------------+
The pin-out file can be found in E:\HILBERT\rader_hilbert3\quartus\rader_hilbert.pin.
+-----------------------------------------------------------------------------+
| Resource Usage Summary |
+-----------------------------------------------------------------------------+
+----------------------------+------------------------+
| Resource | Usage |
+----------------------------+------------------------+
| Logic cells | 295 / 25,660 ( 1 % ) |
| Registers | 242 / 27,451 ( < 1 % ) |
| User inserted logic cells | 0 |
| I/O pins | 51 / 597 ( 8 % ) |
| Clock pins | 1 |
| Dedicated input pins | 0 |
| Global signals | 2 |
| M512s | 0 / 224 ( 0 % ) |
| M4Ks | 0 / 138 ( 0 % ) |
| M-RAMs | 0 / 2 ( 0 % ) |
| Total memory bits | 0 / 1,944,576 ( 0 % ) |
| Total RAM block bits | 0 / 1,944,576 ( 0 % ) |
| DSP block 9-bit elements | 4 / 80 ( 5 % ) |
| PLLs | 0 / 6 ( 0 % ) |
| Global clocks | 2 / 16 ( 12 % ) |
| Regional clocks | 0 / 16 ( 0 % ) |
| Fast regional clocks | 0 / 8 ( 0 % ) |
| DIFFIOCLKs | 0 / 16 ( 0 % ) |
| SERDES transmitters | 0 / 78 ( 0 % ) |
| SERDES receivers | 0 / 78 ( 0 % ) |
| Maximum fan-out node | clk |
| Maximum fan-out | 162 |
| Total fan-out | 939 |
| Average fan-out | 2.68 |
+----------------------------+------------------------+
+-----------------------------------------------------------------------------+
| Resource Utilization by Entity |
+-----------------------------------------------------------------------------+
+------------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
| Compilation Hierarchy Node | Logic Cells | Registers | Memory Bits | DSP Elements | DSP 9x9 | DSP 18x18 | DSP 36x36 | Pins | Virtual Pins | LUT-Only LCs | Register-Only LCs | LUT/Register LCs | Full Hierarchy Name |
+------------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
| |rader_hilbert | 295 (0) | 242 | 0 | 4 | 0 | 2 | 0 | 52 | 0 | 53 (0) | 187 (0) | 55 (0) | |rader_hilbert |
| |adddiv2:inst44| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44 |
| |rd_lpm_add_sub0:lpm_add_sub0_component| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component |
| |lpm_add_sub:lpm_add_sub_component| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component |
| |addcore:adder| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder |
| |a_csnbuffer:result_node| | 17 (17) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (17) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node |
| |contrIQ:inst4| | 3 (3) | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 1 (1) | |rader_hilbert|contrIQ:inst4 |
| |expand:inst17| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 0 (0) | |rader_hilbert|expand:inst17 |
| |expand:inst6| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 0 (0) | |rader_hilbert|expand:inst6 |
| |indatamux:inst| | 32 (0) | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 32 (0) | 0 (0) | |rader_hilbert|indatamux:inst |
| |rh_lpm_dff0:inst1| | 16 (0) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (0) | 0 (0) | |rader_hilbert|indatamux:inst|rh_lpm_dff0:inst1 |
| |lpm_ff:lpm_ff_component| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (16) | 0 (0) | |rader_hilbert|indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component |
| |rh_lpm_dff0:inst| | 16 (0) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (0) | 0 (0) | |rader_hilbert|indatamux:inst|rh_lpm_dff0:inst |
| |lpm_ff:lpm_ff_component| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (16) | 0 (0) | |rader_hilbert|indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component |
| |oesel:inst1| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | |rader_hilbert|oesel:inst1 |
| |rd_contr:inst10| | 7 (7) | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 6 (6) | 1 (1) | |rader_hilbert|rd_contr:inst10 |
| |rd_contract:inst22| | 17 (17) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 9 (9) | |rader_hilbert|rd_contract:inst22 |
| |rd_contract:inst25| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 8 (8) | |rader_hilbert|rd_contract:inst25 |
| |rh_lpm_add_sub1:inst19| | 25 (0) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 17 (0) | |rader_hilbert|rh_lpm_add_sub1:inst19 |
| |lpm_add_sub:lpm_add_sub_component| | 25 (0) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 17 (0) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component |
| |addcore:adder1[0]| | 17 (0) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 9 (0) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0] |
| |a_csnbuffer:result_node| | 17 (17) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (8) | 0 (0) | 9 (9) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node |
| |addcore:adder1_0[1]| | 8 (0) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 8 (0) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1] |
| |a_csnbuffer:result_node| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 8 (8) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node |
| |rh_lpm_add_sub1:inst21| | 25 (0) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 17 (0) | |rader_hilbert|rh_lpm_add_sub1:inst21 |
| |lpm_add_sub:lpm_add_sub_component| | 25 (0) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 17 (0) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component |
| |addcore:adder1[0]| | 17 (0) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 9 (0) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0] |
| |a_csnbuffer:result_node| | 17 (17) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (8) | 0 (0) | 9 (9) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node |
| |addcore:adder1_0[1]| | 8 (0) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 8 (0) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1] |
| |a_csnbuffer:result_node| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 8 (8) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node |
| |rh_lpm_dff0:inst11| | 16 (0) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (0) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst11 |
| |lpm_ff:lpm_ff_component| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (16) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component |
| |rh_lpm_dff0:inst12| | 8 (0) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (0) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst12 |
| |lpm_ff:lpm_ff_component| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst12|lpm_ff:lpm_ff_component |
| |rh_lpm_dff0:inst13| | 16 (0) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (0) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst13 |
| |lpm_ff:lpm_ff_component| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (16) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst13|lpm_ff:lpm_ff_component |
| |rh_lpm_dff0:inst14| | 8 (0) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (0) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst14 |
| |lpm_ff:lpm_ff_component| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst14|lpm_ff:lpm_ff_component |
| |rh_lpm_mult0:inst15| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult0:inst15 |
| |lpm_mult:lpm_mult_component| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component |
| |mult_oam:auto_generated| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_oam:auto_generated |
| |rh_lpm_mult_Q:inst2| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult_Q:inst2 |
| |lpm_mult:lpm_mult_component| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component |
| |mult_oam:auto_generated| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult_Q:inst2|lpm_mult:lpm_mu⌨️ 快捷键说明
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