📄 rader_hilbert.csf.rpt
字号:
bypassff:sign_ff
bypassff:sign_ff[0]
rd_contract:inst22
sw1_4:inst23
subdiv2:inst24
rd_lpm_add_sub2:lpm_add_sub2_component
lpm_add_sub:lpm_add_sub_component
addcore:adder
a_csnbuffer:cout_node
a_csnbuffer:oflow_node
a_csnbuffer:result_node
altshift:carry_ext_latency_ffs
altshift:oflow_ext_latency_ffs
rd_contract:inst25
sw1_4:inst26
adddiv2:inst44
rd_lpm_add_sub0:lpm_add_sub0_component
lpm_add_sub:lpm_add_sub_component
addcore:adder
a_csnbuffer:cout_node
a_csnbuffer:oflow_node
a_csnbuffer:result_node
altshift:carry_ext_latency_ffs
altshift:oflow_ext_latency_ffs
altshift:result_ext_latency_ffs
+-----------------------------------------------------------------------------+
| Logic Options |
+-----------------------------------------------------------------------------+
+-----------------------------------+-------+
| Name | Value |
+-----------------------------------+-------+
| Optimization Technique -- Stratix | Speed |
| Power-Up Don't Care | On |
+-----------------------------------+-------+
+-----------------------------------------------------------------------------+
| Resource Utilization by Entity |
+-----------------------------------------------------------------------------+
+------------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
| Compilation Hierarchy Node | Logic Cells | Registers | Memory Bits | DSP Elements | DSP 9x9 | DSP 18x18 | DSP 36x36 | Pins | Virtual Pins | LUT-Only LCs | Register-Only LCs | LUT/Register LCs | Full Hierarchy Name |
+------------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
| |rader_hilbert | 299 (0) | 242 | 0 | 4 | 0 | 2 | 0 | 51 | 0 | 57 (0) | 191 (0) | 51 (0) | |rader_hilbert |
| |adddiv2:inst44| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44 |
| |rd_lpm_add_sub0:lpm_add_sub0_component| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component |
| |lpm_add_sub:lpm_add_sub_component| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component |
| |addcore:adder| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder |
| |a_csnbuffer:result_node| | 17 (17) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (17) | 0 (0) | 0 (0) | |rader_hilbert|adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node |
| |contrIQ:inst4| | 3 (3) | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 3 (3) | 0 (0) | |rader_hilbert|contrIQ:inst4 |
| |expand:inst17| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 0 (0) | |rader_hilbert|expand:inst17 |
| |expand:inst6| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 0 (0) | |rader_hilbert|expand:inst6 |
| |indatamux:inst| | 32 (0) | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 32 (0) | 0 (0) | |rader_hilbert|indatamux:inst |
| |rh_lpm_dff0:inst1| | 16 (0) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (0) | 0 (0) | |rader_hilbert|indatamux:inst|rh_lpm_dff0:inst1 |
| |lpm_ff:lpm_ff_component| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (16) | 0 (0) | |rader_hilbert|indatamux:inst|rh_lpm_dff0:inst1|lpm_ff:lpm_ff_component |
| |rh_lpm_dff0:inst| | 16 (0) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (0) | 0 (0) | |rader_hilbert|indatamux:inst|rh_lpm_dff0:inst |
| |lpm_ff:lpm_ff_component| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (16) | 0 (0) | |rader_hilbert|indatamux:inst|rh_lpm_dff0:inst|lpm_ff:lpm_ff_component |
| |oesel:inst1| | 3 (3) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 1 (1) | 1 (1) | |rader_hilbert|oesel:inst1 |
| |rd_contr:inst10| | 7 (7) | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 7 (7) | 0 (0) | |rader_hilbert|rd_contr:inst10 |
| |rd_contract:inst22| | 18 (18) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 9 (9) | 8 (8) | |rader_hilbert|rd_contract:inst22 |
| |rd_contract:inst25| | 17 (17) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 8 (8) | 8 (8) | |rader_hilbert|rd_contract:inst25 |
| |rh_lpm_add_sub1:inst19| | 25 (0) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 17 (0) | |rader_hilbert|rh_lpm_add_sub1:inst19 |
| |lpm_add_sub:lpm_add_sub_component| | 25 (0) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 17 (0) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component |
| |addcore:adder1[0]| | 17 (0) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 9 (0) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0] |
| |a_csnbuffer:result_node| | 17 (17) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (8) | 0 (0) | 9 (9) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node |
| |addcore:adder1_0[1]| | 8 (0) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 8 (0) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1] |
| |a_csnbuffer:result_node| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 8 (8) | |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node |
| |rh_lpm_add_sub1:inst21| | 25 (0) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 17 (0) | |rader_hilbert|rh_lpm_add_sub1:inst21 |
| |lpm_add_sub:lpm_add_sub_component| | 25 (0) | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 17 (0) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component |
| |addcore:adder1[0]| | 17 (0) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (0) | 0 (0) | 9 (0) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0] |
| |a_csnbuffer:result_node| | 17 (17) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (8) | 0 (0) | 9 (9) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node |
| |addcore:adder1_0[1]| | 8 (0) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 8 (0) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1] |
| |a_csnbuffer:result_node| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 8 (8) | |rader_hilbert|rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node |
| |rh_lpm_dff0:inst11| | 16 (0) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (0) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst11 |
| |lpm_ff:lpm_ff_component| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (16) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component |
| |rh_lpm_dff0:inst12| | 8 (0) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (0) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst12 |
| |lpm_ff:lpm_ff_component| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst12|lpm_ff:lpm_ff_component |
| |rh_lpm_dff0:inst13| | 16 (0) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (0) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst13 |
| |lpm_ff:lpm_ff_component| | 16 (16) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 16 (16) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst13|lpm_ff:lpm_ff_component |
| |rh_lpm_dff0:inst14| | 8 (0) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (0) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst14 |
| |lpm_ff:lpm_ff_component| | 8 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 8 (8) | 0 (0) | |rader_hilbert|rh_lpm_dff0:inst14|lpm_ff:lpm_ff_component |
| |rh_lpm_mult0:inst15| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult0:inst15 |
| |lpm_mult:lpm_mult_component| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component |
| |mult_oam:auto_generated| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult0:inst15|lpm_mult:lpm_mult_component|mult_oam:auto_generated |
| |rh_lpm_mult_Q:inst2| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult_Q:inst2 |
| |lpm_mult:lpm_mult_component| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component |
| |mult_oam:auto_generated| | 0 (0) | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | |rader_hilbert|rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_oam:auto_generated |
| |subdiv2:inst24| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|subdiv2:inst24 |
| |rd_lpm_add_sub2:lpm_add_sub2_component| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component |
| |lpm_add_sub:lpm_add_sub_component| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component |
| |addcore:adder| | 17 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (0) | 0 (0) | 0 (0) | |rader_hilbert|subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component|addcore:adder |
| |a_csnbuffer:result_node| | 17 (17) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (17) | 0 (0) | 0 (0) | |rader_hilbert|subdiv2:inst24|rd_lpm_add_sub2:lpm_add_sub2_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node |
| |sw1_4:inst23| | 35 (35) | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 (2) | 33 (33) | 0 (0) | |rader_hilbert|sw1_4:inst23 |
| |sw1_4:inst26| | 36 (36) | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 (2) | 34 (34) | 0 (0) | |rader_hilbert|sw1_4:inst26 |
+------------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------+
| Device Options |
+-----------------------------------------------------------------------------+
+------------------------------------------------------------------+--------------------------+
| Option | Setting |
+------------------------------------------------------------------+--------------------------+
| Auto-restart configuration after error | Off |
| Release clears before tri-states | Off |
| Enable user-supplied start-up clock (CLKUSR) | Off |
| Enable device-wide reset (DEV_CLRn) | Off |
| Enable device-wide output enable (DEV_OE) | Off |
| Enable INIT_DONE output | Off |
| Auto-increment JTAG user code for multiple configuration devices | On |
| Disable CONF_DONE and nSTATUS pull-ups on configuration device | Off |
| Generate compressed bitstreams | Off |
| Generate Tabular Text File (.ttf) | Off |
| Generate Raw Binary File (.rbf) | Off |
| Generate Hexadecimal Output File (.hexout) | Off |
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