rader_hilbert.csf.rpt

FPGA开发光盘各章节实例的设计工程与源码

  Info: 2: + IC(0.888 ns) + CELL(0.344 ns) = 1.232 ns; Loc. = LAB_X67_Y25; COMB Node = 'adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~COUT0'
  Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 1.290 ns; Loc. = LAB_X67_Y25; COMB Node = 'adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~COUT0'
  Info: 4: + IC(0.000 ns) + CELL(0.214 ns) = 1.504 ns; Loc. = LAB_X67_Y25; COMB Node = 'adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cout[2]'
  Info: 5: + IC(0.000 ns) + CELL(0.469 ns) = 1.973 ns; Loc. = LAB_X67_Y25; COMB Node = 'adddiv2:inst44|rd_lpm_add_sub0:lpm_add_sub0_component|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]'
  Info: 6: + IC(1.129 ns) + CELL(3.451 ns) = 6.553 ns; Loc. = DSPMULT_X68_Y23_N0; COMB Node = 'rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_oam:auto_generated|mac_mult2'
  Info: 7: + IC(0.000 ns) + CELL(0.878 ns) = 7.431 ns; Loc. = DSPOUT_X69_Y17_N0; COMB Node = 'rh_lpm_mult_Q:inst2|lpm_mult:lpm_mult_component|mult_oam:auto_generated|result[8]'
  Info: 8: + IC(0.953 ns) + CELL(0.344 ns) = 8.728 ns; Loc. = LAB_X70_Y23; COMB Node = 'rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[8]~COUT0'
  Info: 9: + IC(0.000 ns) + CELL(0.058 ns) = 8.786 ns; Loc. = LAB_X70_Y23; COMB Node = 'rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[9]~COUT0'
  Info: 10: + IC(0.000 ns) + CELL(0.058 ns) = 8.844 ns; Loc. = LAB_X70_Y23; COMB Node = 'rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]~COUT0'
  Info: 11: + IC(0.000 ns) + CELL(0.058 ns) = 8.902 ns; Loc. = LAB_X70_Y23; COMB Node = 'rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[11]~COUT0'
  Info: 12: + IC(0.000 ns) + CELL(0.214 ns) = 9.116 ns; Loc. = LAB_X70_Y23; COMB Node = 'rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|cout[12]'
  Info: 13: + IC(0.000 ns) + CELL(0.598 ns) = 9.714 ns; Loc. = LAB_X70_Y23; REG Node = 'rh_lpm_add_sub1:inst21|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[16]'
  Info: Total cell delay = 6.744 ns
  Info: Total interconnect delay = 2.970 ns
Warning: Found pins functioning as undefined clocks and/or memory enables
  Info: Assuming node clk is an undefined clock
Warning: Circuit may not operate. 32 non-operational path(s) clocked by clock clk have clock skew larger than the data delay. See the Compilation Report for details.
Info: Found hold time violation between source  pin or register rd_contract:inst22|wconout[7]~reg0 and destination pin or register rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[7] for clock clk (Hold time is 2.733 ns)
  Info: + Largest clock skew is 3.394 ns
    Info: + Longest clock path from clock clk to destination register is 6.376 ns
      Info: 1: + IC(0.000 ns) + CELL(0.732 ns) = 0.732 ns; Loc. = Pin_R25; CLK Node = 'clk'
      Info: 2: + IC(1.697 ns) + CELL(0.698 ns) = 3.127 ns; Loc. = LC_X1_Y25_N5; REG Node = 'oesel:inst1|odden~reg0'
      Info: 3: + IC(2.707 ns) + CELL(0.542 ns) = 6.376 ns; Loc. = LC_X12_Y20_N1; REG Node = 'rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[7]'
      Info: Total cell delay = 1.972 ns
      Info: Total interconnect delay = 4.404 ns
    Info: - Shortest clock path from clock clk to source register is 2.982 ns
      Info: 1: + IC(0.000 ns) + CELL(0.732 ns) = 0.732 ns; Loc. = Pin_R25; CLK Node = 'clk'
      Info: 2: + IC(1.708 ns) + CELL(0.542 ns) = 2.982 ns; Loc. = LC_X12_Y20_N4; REG Node = 'rd_contract:inst22|wconout[7]~reg0'
      Info: Total cell delay = 1.274 ns
      Info: Total interconnect delay = 1.708 ns
  Info: - Micro clock to output delay of source is 0.156 ns
  Info: - Shortest register to register delay is 0.605 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y20_N4; REG Node = 'rd_contract:inst22|wconout[7]~reg0'
    Info: 2: + IC(0.382 ns) + CELL(0.223 ns) = 0.605 ns; Loc. = LC_X12_Y20_N1; REG Node = 'rh_lpm_dff0:inst11|lpm_ff:lpm_ff_component|dffs[7]'
    Info: Total cell delay = 0.223 ns
    Info: Total interconnect delay = 0.382 ns
  Info: + Micro hold delay of destination is 0.100 ns

+-----------------------------------------------------------------------------+
| Hierarchy                                                                   |
+-----------------------------------------------------------------------------+
Hierarchy
  rader_hilbert
    indatamux:inst
      rh_lpm_dff0:inst
        lpm_ff:lpm_ff_component
      rh_lpm_dff0:inst1
        lpm_ff:lpm_ff_component
    oesel:inst1
    rh_lpm_mult_Q:inst2
      lpm_mult:lpm_mult_component
        mult_oam:auto_generated
    contrIQ:inst4
    expand:inst6
    rd_contr:inst10
    rh_lpm_dff0:inst11
      lpm_ff:lpm_ff_component
    rh_lpm_dff0:inst12
      lpm_ff:lpm_ff_component
    rh_lpm_dff0:inst13
      lpm_ff:lpm_ff_component
    rh_lpm_dff0:inst14
      lpm_ff:lpm_ff_component
    rh_lpm_mult0:inst15
      lpm_mult:lpm_mult_component
        mult_oam:auto_generated
    expand:inst17
    rh_lpm_add_sub1:inst19
      lpm_add_sub:lpm_add_sub_component
        addcore:adder1
        addcore:adder1[0]
          a_csnbuffer:oflow_node
          a_csnbuffer:result_node
        addcore:adder1[1]
          a_csnbuffer:cout_node
          a_csnbuffer:result_node
        addcore:adder1_0
        addcore:adder1_0[1]
          a_csnbuffer:cout_node
          a_csnbuffer:oflow_node
          a_csnbuffer:result_node
        bypassff:datab1_ff
        bypassff:datab1_ff[0]
        bypassff:datab1_ff[0][0]
        bypassff:datab1_ff[1]
        bypassff:datab1_ff[1][0]
        altshift:oflow_ext_latency_ffs
    rh_lpm_add_sub1:inst21
      lpm_add_sub:lpm_add_sub_component
        addcore:adder1
        addcore:adder1[0]
          a_csnbuffer:cout_node
          a_csnbuffer:oflow_node
          a_csnbuffer:result_node
        addcore:adder1[1]
          a_csnbuffer:cout_node
          a_csnbuffer:oflow_node
          a_csnbuffer:result_node
        addcore:adder1_0
        addcore:adder1_0[1]
          a_csnbuffer:cout_node
          a_csnbuffer:oflow_node
          a_csnbuffer:result_node
        altshift:carry_ext_latency_ffs
        bypassff:datab1_ff
        bypassff:datab1_ff[0]
        bypassff:datab1_ff[0][0]
        bypassff:datab1_ff[0][1]
        bypassff:datab1_ff[1]
        bypassff:datab1_ff[1][0]
        bypassff:datab1_ff[1][1]
        altshift:oflow_ext_latency_ffs
        altshift:result_ext_latency_ffs