rader_hilbert.csf.rpt

FPGA开发光盘各章节实例的设计工程与源码

| Option                                                   | Setting            |
+----------------------------------------------------------+--------------------+
| Chip name                                                | rader_hilbert      |
| Family name                                              | Stratix            |
| Focus entity name                                        | |rader_hilbert     |
| Device                                                   | EP1S25F780C5       |
| Disk space/compilation speed tradeoff                    | Normal             |
| Preserve fewer node names                                | On                 |
| Optimize timing                                          | Normal Compilation |
| Optimize IOC register placement for timing               | On                 |
| Fast Fit compilation                                     | Off                |
| Perform WYSIWYG primitive resynthesis                    | Off                |
| Perform gate-level register retiming                     | Off                |
| Use Fitter timing information during synthesis           | Off                |
| Duplicate logic elements during fitting                  | Off                |
| Duplicate logic elements/resythesize LUTs during fitting | Off                |
| SignalProbe compilation                                  | Off                |
| Generate compressed bitstreams                           | Off                |
+----------------------------------------------------------+--------------------+

+-----------------------------------------------------------------------------+
| Messages                                                                    |
+-----------------------------------------------------------------------------+
Info: Found 1 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rd_contr.bdf
  Info: Found entity 1: rd_contr
Info: Found 1 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\contrIQ.bdf
  Info: Found entity 1: contrIQ
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\oesel.vhd
  Info: Found design unit 1: oesel-behv
  Info: Found entity 1: oesel
Info: Found 1 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\indatamux.bdf
  Info: Found entity 1: indatamux
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rh_lpm_dff0.vhd
  Info: Found design unit 1: rh_lpm_dff0-syn
  Info: Found entity 1: rh_lpm_dff0
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\subdiv2.vhd
  Info: Found design unit 1: subdiv2-behv
  Info: Found entity 1: subdiv2
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\adddiv2.vhd
  Info: Found design unit 1: adddiv2-behv
  Info: Found entity 1: adddiv2
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rh_lpm_add_sub1.vhd
  Info: Found design unit 1: rh_lpm_add_sub1-syn
  Info: Found entity 1: rh_lpm_add_sub1
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rd_contract.vhd
  Info: Found design unit 1: rd_contract-behv
  Info: Found entity 1: rd_contract
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rh_lpm_mult0.vhd
  Info: Found design unit 1: rh_lpm_mult0-syn
  Info: Found entity 1: rh_lpm_mult0
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\expand.vhd
  Info: Found design unit 1: expand-behv
  Info: Found entity 1: expand
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\sw1_4.vhd
  Info: Found design unit 1: sw1_4-behv
  Info: Found entity 1: sw1_4
Info: Found 1 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rader_hilbert.bdf
  Info: Found entity 1: rader_hilbert
Info: Found 1 design units and 1 entities in source file D:\quartus\libraries\megafunctions\lpm_add_sub.tdf
  Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file D:\quartus\libraries\megafunctions\addcore.tdf
  Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file D:\quartus\libraries\megafunctions\a_csnbuffer.tdf
  Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file D:\quartus\libraries\megafunctions\bypassff.tdf
  Info: Found entity 1: bypassff
Info: Found 1 design units and 1 entities in source file D:\quartus\libraries\megafunctions\altshift.tdf
  Info: Found entity 1: altshift
Info: Found 1 design units and 1 entities in source file D:\quartus\libraries\megafunctions\lpm_mult.tdf
  Info: Found entity 1: lpm_mult
Info: Found 1 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\db\mult_oam.tdf
  Info: Found entity 1: mult_oam
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rd_lpm_add_sub2.vhd
  Info: Found design unit 1: rd_lpm_add_sub2-syn
  Info: Found entity 1: rd_lpm_add_sub2
Info: Found 1 design units and 1 entities in source file D:\quartus\libraries\megafunctions\lpm_ff.tdf
  Info: Found entity 1: lpm_ff
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rh_lpm_mult_Q.vhd
  Info: Found design unit 1: rh_lpm_mult_q-syn
  Info: Found entity 1: rh_lpm_mult_q
Info: Found 2 design units and 1 entities in source file E:\HILBERT\rader_hilbert3\quartus\rd_lpm_add_sub0.vhd
  Info: Found design unit 1: rd_lpm_add_sub0-syn
  Info: Found entity 1: rd_lpm_add_sub0
Info: Duplicate registers merged to single register
  Info: Duplicate registers merged to single register oesel:inst1|evenen~reg0, power-up level has changed
  Info: Duplicate registers merged to single register oesel:inst1|latchcnt
  Info: Duplicate registers merged to single register contrIQ:inst4|inst32
  Info: Duplicate registers merged to single register sw1_4:inst23|ad_clk1, power-up level has changed
  Info: Duplicate registers merged to single register contrIQ:inst4|inst38, power-up level has changed
  Info: Duplicate registers merged to single register rd_contr:inst10|inst6
  Info: Duplicate registers merged to single register contrIQ:inst4|inst19, power-up level has changed
  Info: Duplicate registers merged to single register contrIQ:inst4|inst35, power-up level has changed
  Info: Duplicate registers merged to single register contrIQ:inst4|inst41, power-up level has changed
  Info: Duplicate registers merged to single register rd_contract:inst25|conclk1, power-up level has changed
Warning: LCELL atom odden~reg0 has regout port that feeds clock signal input port of another atom
Info: Implemented 354 device resources
  Info: Implemented 18 input pins
  Info: Implemented 33 output pins
  Info: Implemented 299 logic cells
  Info: Implemented 4 DSP elements
Info: Selected device EP1S25F780C5 for design rader_hilbert
Info: Smart compilation specified to OFF -- SignalProbe information will not be saved
Info: Automatically promoted signal clk to use Global clock in Pin R25
Info: Automatically promoted some destinations of signal oesel:inst1|odden~reg0 to use Global clock
  Info: Destination oesel:inst1|odden~reg0 may be non-global or may not use global clock
  Info: Destination sw1_4:inst26|ad_clk1 may be non-global or may not use global clock
  Info: Destination sw1_4:inst26|temp[15]~0 may be non-global or may not use global clock
  Info: Destination sw1_4:inst23|temp[15]~0 may be non-global or may not use global clock
  Info: Destination sw1_4:inst26|i~1 may be non-global or may not use global clock
  Info: Destination sw1_4:inst23|i~1 may be non-global or may not use global clock
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 9.714 ns
  Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X71_Y25; REG Node = 'rh_lpm_dff0:inst13|lpm_ff:lpm_ff_component|dffs[0]'