rader_hilbert.csf.rpt

FPGA开发光盘各章节实例的设计工程与源码

rader_hilbert - Quartus II Compilation Report File
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| Report Information                                                                 |
+--------------------+---------------------------------------------------------------+
| Project            | E:\HILBERT\rader_hilbert3\quartus/                            |
| Compiler Settings  | rader_hilbert                                                 |
| Quartus II Version | 2.2 Build 191 03/31/2003 SP 2 SJ Full Version                 |
+--------------------+---------------------------------------------------------------+

Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "rader_hilbert" Compiler Settings
            Summary
            Compiler Settings
            Messages
            Hierarchy
            Logic Options
            Synthesis Section
                Resource Utilization by Entity
            Device Options
            Equations
            Floorplan View
            Pin-Out File
            Resource Section
                Resource Usage Summary
                Resource Utilization by Entity
                Input Pins
                Output Pins
                Delay Chain Summary
                I/O Bank Usage
                All Package Pins
                Control Signals
                Global & Other Fast Signals
                Non-Global High Fan-Out Signals
                DSP Block Usage Summary
                DSP Block Details
                Output Pin Load For Reported TCO
                LAB and Routing Section
                    Interconnect Usage Summary
                    LAB Logic Elements
                    LAB-wide Signals
                    LAB Signals Sourced
                    LAB Signals Sourced Out
                    LAB Distinct Inputs
            Timing Analyses
                Timing Settings
                fmax (not incl. delays to/from pins)
                Register-to-Register fmax
                tsu (Input Setup Times)
                th (Input Hold Times)
                tco (Clock to Output Delays)
            Processing Time

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| Legal Notice                                                                |
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Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
| General Settings                                                            |
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+-------------------+---------------------+
| Option            | Setting             |
+-------------------+---------------------+
| Start date & time | 12/16/2003 11:17:13 |
| Main task         | Compilation         |
| Settings name     | rader_hilbert       |
+-------------------+---------------------+

+-----------------------------------------------------------------------------+
| Summary                                                                     |
+-----------------------------------------------------------------------------+
+-------------------------------------+-----------------------------------------------+
| Processing status                   | Fitting Successful - Tue Dec 16 11:19:34 2003 |
| Timing requirements/analysis status | Circuit will not operate                      |
| Chip name                           | rader_hilbert                                 |
| Device for compilation              | EP1S25F780C5                                  |
| Total logic elements                | 295 / 25,660 ( 1 % )                          |
| Total pins                          | 51 / 597 ( 8 % )                              |
| Total memory bits                   | 0 / 1,944,576 ( 0 % )                         |
| DSP block 9-bit elements            | 4 / 80 ( 5 % )                                |
| Total PLLs                          | 0 / 6 ( 0 % )                                 |
| Device for timing analysis          | EP1S25F780C5                                  |
+-------------------------------------+-----------------------------------------------+

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| Compiler Settings                                                           |
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