rader_hilbert.sim.rpt

FPGA开发光盘各章节实例的设计工程与源码

; |rader_hilbert|rd_contract:inst25|wconout[9]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[9]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[9]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[9]~526                                                                                                                       ; cout0            ;
; |rader_hilbert|rd_contract:inst25|wconout[9]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[9]~526COUT1_546                                                                                                              ; cout1            ;
; |rader_hilbert|rd_contract:inst25|wconout[8]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[8]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[8]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[8]~527                                                                                                                       ; cout0            ;
; |rader_hilbert|rd_contract:inst25|wconout[8]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[8]~527COUT1_544                                                                                                              ; cout1            ;
; |rader_hilbert|rd_contract:inst25|wconout[7]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[7]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[6]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[6]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[5]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[5]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[4]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[4]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[3]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[3]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[2]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[2]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[1]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[1]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contract:inst25|wconout[0]                                                                                                                  ; |rader_hilbert|rd_contract:inst25|wconout[0]                                                                                                                           ; regout           ;
; |rader_hilbert|rd_contr:inst10|inst12                                                                                                                         ; |rader_hilbert|rd_contr:inst10|inst12                                                                                                                                  ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]                                       ; regout           ;
; |rader_hilbert|contrIQ:inst4|inst41                                                                                                                           ; |rader_hilbert|contrIQ:inst4|inst41                                                                                                                                    ; regout           ;
; |rader_hilbert|rd_contract:inst22|conclk1                                                                                                                     ; |rader_hilbert|rd_contract:inst22|conclk1                                                                                                                              ; regout           ;
; |rader_hilbert|rd_contract:inst22|process0~0                                                                                                                  ; |rader_hilbert|rd_contract:inst22|process0~0                                                                                                                           ; combout          ;
; |rader_hilbert|rd_contr:inst10|inst3                                                                                                                          ; |rader_hilbert|rd_contr:inst10|inst3                                                                                                                                   ; regout           ;
; |rader_hilbert|oesel:inst1|hlmux1                                                                                                                             ; |rader_hilbert|oesel:inst1|hlmux1                                                                                                                                      ; regout           ;
; |rader_hilbert|rd_contr:inst10|inst                                                                                                                           ; |rader_hilbert|rd_contr:inst10|inst                                                                                                                                    ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]                                       ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]~33                                    ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]~33COUT1_58                            ; cout1            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]                                       ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]~34                                    ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[5]~34COUT1_56                            ; cout1            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]                                       ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[4]~35                                    ; cout             ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]                                       ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~36                                    ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]~36COUT1_54                            ; cout1            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]                                       ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~37                                    ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[2]~37COUT1_52                            ; cout1            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]                                       ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~38                                    ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[1]~38COUT1_50                            ; cout1            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]                                       ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~39                                    ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]                              ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]~39COUT1_48                            ; cout1            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[16]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[16]                                        ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]                                        ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]~85                                     ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[15]~85COUT1_166                            ; cout1            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[14]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[14]                                        ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[14]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[14]~86                                     ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[14]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[14]~86COUT1_164                            ; cout1            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13]                                        ; regout           ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13]                               ; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13]~87                                     ; cout0            ;
; |rader_hilbert|rh_lpm_add_sub1:inst19|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[13]                               ;